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Reel/Frame:037961/0519   Pages: 7
Recorded: 03/01/2016
Attorney Dkt #:MSMI CHANGE OF NAME
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 37
1
Patent #:
Issue Dt:
10/11/2016
Application #:
12200062
Filing Dt:
08/28/2008
Publication #:
Pub Dt:
03/04/2010
Title:
Method of Tracking Arrival Order of Packets into Plural Queues
2
Patent #:
Issue Dt:
04/22/2014
Application #:
13023336
Filing Dt:
02/08/2011
Title:
NONVOLATILE MEMORY CONTROLLER WITH TWO-STAGE ERROR CORRECTION TECHNIQUE FOR ENHANCED RELIABILITY
3
Patent #:
Issue Dt:
11/19/2013
Application #:
13052008
Filing Dt:
03/18/2011
Title:
NONVOLATILE MEMORY CONTROLLER WITH HOST CONTROLLER INTERFACE FOR RETRIEVING AND DISPATCHING NONVOLATILE MEMORY COMMANDS IN A DISTRIBUTED MANNER
4
Patent #:
Issue Dt:
10/08/2013
Application #:
13052388
Filing Dt:
03/21/2011
Title:
INTERRUPT TECHNIQUE FOR A NONVOLATILE MEMORY CONTROLLER
5
Patent #:
Issue Dt:
12/03/2013
Application #:
13052835
Filing Dt:
03/21/2011
Title:
SYSTEM AND METHOD FOR GENERATING PARITY DATA IN A NONVOLATILE MEMORY CONTROLLER BY USING A DISTRIBUTED PROCESSING TECHNIQUE
6
Patent #:
Issue Dt:
02/18/2014
Application #:
13107265
Filing Dt:
05/13/2011
Title:
SYSTEM AND METHOD FOR ROUTING A DATA MESSAGE THROUGH A MESSAGE NETWORK
7
Patent #:
Issue Dt:
11/21/2017
Application #:
13159330
Filing Dt:
06/13/2011
Title:
Apparatus and Method to Adjust Power and Performance of Integrated Circuits
8
Patent #:
Issue Dt:
12/03/2013
Application #:
13195685
Filing Dt:
08/01/2011
Title:
DATA REGENERATION APPARATUS AND METHOD FOR PCI EXPRESS
9
Patent #:
Issue Dt:
04/08/2014
Application #:
13287443
Filing Dt:
11/02/2011
Title:
ERROR CORRECTION CODE TECHNIQUE FOR IMPROVING READ STRESS ENDURANCE
10
Patent #:
Issue Dt:
04/08/2014
Application #:
13330573
Filing Dt:
12/19/2011
Title:
SHUFFLER ERROR CORRECTION CODE SYSTEM AND METHOD
11
Patent #:
Issue Dt:
02/18/2014
Application #:
13434770
Filing Dt:
03/29/2012
Title:
NONVOLATILE MEMORY CONTROLLER WITH CONCATENATED ERROR CORRECTION CODES
12
Patent #:
Issue Dt:
12/31/2013
Application #:
13435572
Filing Dt:
03/30/2012
Title:
NONVOLATILE MEMORY CONTROLLER WITH ERROR DETECTION FOR CONCATENATED ERROR CORRECTION CODES
13
Patent #:
Issue Dt:
12/23/2014
Application #:
13681257
Filing Dt:
11/19/2012
Title:
METHOD AND APPARATUS FOR AN AGGREGATED NON-TRANSPARENT REQUESTER ID TRANSLATION FOR A PCIE SWITCH
14
Patent #:
Issue Dt:
05/05/2015
Application #:
13743225
Filing Dt:
01/16/2013
Title:
FLEXIBLE ROUTING ENGINE FOR A PCI EXPRESS SWITCH AND METHOD OF USE
15
Patent #:
Issue Dt:
03/31/2015
Application #:
13743281
Filing Dt:
01/16/2013
Title:
METHOD AND APPARATUS FOR TRANSLATED ROUTING IN AN INTERCONNECT SWITCH
16
Patent #:
Issue Dt:
09/29/2015
Application #:
13750991
Filing Dt:
01/25/2013
Title:
METHOD AND APPARATUS FOR MAPPED I/O ROUTING IN AN INTERCONNECT SWITCH
17
Patent #:
Issue Dt:
09/08/2015
Application #:
13752757
Filing Dt:
01/29/2013
Title:
APPARATUS AND METHOD FOR ADJUSTING A CORRECTABLE RAW BIT ERROR RATE LIMIT IN A MEMORY SYSTEM USING STRONG LOG-LIKELIHOOD (LLR) VALUES
18
Patent #:
Issue Dt:
07/28/2015
Application #:
13752885
Filing Dt:
01/29/2013
Title:
APPARATUS AND METHOD BASED ON LDPC CODES FOR ADJUSTING A CORRECTABLE RAW BIT ERROR RATE LIMIT IN A MEMORY SYSTEM
19
Patent #:
Issue Dt:
03/24/2015
Application #:
13785848
Filing Dt:
03/05/2013
Title:
LAYER SPECIFIC ATTENUATION FACTOR LDPC DECODER
20
Patent #:
Issue Dt:
07/19/2016
Application #:
13792831
Filing Dt:
03/11/2013
Title:
SYSTEM AND METHOD FOR LIFETIME SPECIFIC LDPC DECODING
21
Patent #:
Issue Dt:
01/13/2015
Application #:
13797444
Filing Dt:
03/12/2013
Title:
SYSTEM AND METHOD FOR ADAPTIVE CHECK NODE APPROXIMATION IN LDPC DECODING
22
Patent #:
Issue Dt:
03/17/2015
Application #:
13860300
Filing Dt:
04/10/2013
Title:
SYSTEM AND METHOD FOR REDUCED MEMORY STORAGE IN LDPC DECODING
23
Patent #:
Issue Dt:
03/17/2015
Application #:
13860411
Filing Dt:
04/10/2013
Title:
SYSTEM AND METHOD FOR AVOIDING ERROR MECHANISMS IN LAYERED ITERATIVE DECODING
24
Patent #:
Issue Dt:
01/12/2016
Application #:
14165135
Filing Dt:
01/27/2014
Publication #:
Pub Dt:
09/18/2014
Title:
SYSTEM AND METHOD WITH REFERENCE VOLTAGE PARTITIONING FOR LOW DENSITY PARITY CHECK DECODING
25
Patent #:
Issue Dt:
01/12/2016
Application #:
14168222
Filing Dt:
01/30/2014
Publication #:
Pub Dt:
09/18/2014
Title:
SYSTEM AND METHOD FOR RANDOM NOISE GENERATION
26
Patent #:
Issue Dt:
03/07/2017
Application #:
14210067
Filing Dt:
03/13/2014
Publication #:
Pub Dt:
09/18/2014
Title:
SYSTEM AND METHOD FOR HIGHER QUALITY LOG LIKELIHOOD RATIOS IN LDPC DECODING
27
Patent #:
Issue Dt:
09/27/2016
Application #:
14210971
Filing Dt:
03/14/2014
Publication #:
Pub Dt:
09/18/2014
Title:
SYSTEM AND METHOD FOR ACCUMULATING SOFT INFORMATION IN LDPC DECODING
28
Patent #:
Issue Dt:
08/16/2016
Application #:
14325212
Filing Dt:
07/07/2014
Publication #:
Pub Dt:
01/07/2016
Title:
SYSTEM AND METHOD FOR MEMORY BLOCK POOL WEAR LEVELING
29
Patent #:
Issue Dt:
04/05/2016
Application #:
14475757
Filing Dt:
09/03/2014
Publication #:
Pub Dt:
03/03/2016
Title:
NONVOLATILE MEMORY SYSTEM THAT USES PROGRAMMING TIME TO REDUCE BIT ERRORS
30
Patent #:
Issue Dt:
09/20/2016
Application #:
14557214
Filing Dt:
12/01/2014
Title:
HIGH QUALITY LOG LIKELIHOOD RATIOS DETERMINED USING TWO-INDEX LOOK-UP TABLE
31
Patent #:
Issue Dt:
05/17/2016
Application #:
14605884
Filing Dt:
01/26/2015
Title:
PARALLEL REPLICA CDR TO CORRECT OFFSET AND GAIN IN A BAUD RATE SAMPLING PHASE DETECTOR
32
Patent #:
Issue Dt:
10/25/2016
Application #:
14694986
Filing Dt:
04/23/2015
Title:
APPARATUS AND METHOD FOR MINIMIZING EXCLUSIVE-OR (XOR) COMPUTATION TIME
33
Patent #:
Issue Dt:
06/25/2019
Application #:
14715403
Filing Dt:
05/18/2015
Title:
NONVOLATILE MEMORY SYSTEM WITH RETENTION MONITOR
34
Patent #:
Issue Dt:
11/07/2017
Application #:
14747042
Filing Dt:
06/23/2015
Title:
LAYER SPECIFIC LDPC DECODER
35
Patent #:
Issue Dt:
09/20/2016
Application #:
14747952
Filing Dt:
06/23/2015
Title:
MEMORY CONTROLLER AND INTEGRATED CIRCUIT DEVICE FOR CORRECTING ERRORS IN DATA READ FROM MEMORY CELLS
36
Patent #:
Issue Dt:
10/24/2017
Application #:
14812891
Filing Dt:
07/29/2015
Title:
NONVOLATILE MEMORY SYSTEM WITH READ CIRCUIT FOR PERFORMING READS USING THRESHOLD VOLTAGE SHIFT READ INSTRUCTION
37
Patent #:
Issue Dt:
02/20/2018
Application #:
15042125
Filing Dt:
02/11/2016
Publication #:
Pub Dt:
07/27/2017
Title:
NONVOLATILE MEMORY SYSTEM WITH PROGRAM STEP MANAGER AND METHOD FOR PROGRAM STEP MANAGEMENT
Assignor
1
Exec Dt:
01/15/2016
Assignee
1
2711 CENTERVILLE ROAD
SUITE 400
WILMINGTON, DELAWARE 19808
Correspondence name and address
GLASS & ASSOCIATES
P.O. BOX 1220
LOS GATOS, CA 95031-1220

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