Patent Assignment Details
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| Reel/Frame: | 018424/0520 | |
| Pages: | 4 |
| | Recorded: | 10/23/2006 | | |
| Attorney Dkt #: | 2006.06.016.WS0/150.015 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11551940
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Filing Dt:
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10/23/2006
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Publication #:
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Pub Dt:
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05/15/2008
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Title:
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METHOD AND SYSTEM FOR TEST VERIFICATION OF INTEGRATED CIRCUIT DESIGNS CONTAINING AN ANALOG AND A DIGITAL PORTION
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Assignee
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| 416 MAETAN-DONG, PALDAL-GU |
| SUWON-CITY, KYUNGKI-DO, KOREA, REPUBLIC OF |
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Correspondence name and address
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DAVID N. FOGG
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P.O. BOX 581339
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MINNEAPOLIS, MN 55458-1339
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