Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 061309/0527 | |
| Pages: | 21 |
| | Recorded: | 10/04/2022 | | |
| Conveyance: | SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
5
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
17649975
|
Filing Dt:
|
02/04/2022
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2022
| | | | |
|
Title:
|
MEMORY-BASED DISTRIBUTED PROCESSOR ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2024
|
Application #:
|
17668240
|
Filing Dt:
|
02/09/2022
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2022
| | | | |
|
Title:
|
COMPENSATING FOR DRAM ACTIVATION PENALTIES
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
17669642
|
Filing Dt:
|
02/11/2022
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2022
| | | | |
|
Title:
|
CYBER SECURITY AND TAMPER DETECTION TECHNIQUES WITH A DISTRIBUTED PROCESSOR MEMORY CHIP
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
17669649
|
Filing Dt:
|
02/11/2022
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2022
| | | | |
|
Title:
|
DISTRIBUTED PROCESSOR MEMORY CHIP WITH MULTI-PORT PROCESSOR SUBUNITS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
17669657
|
Filing Dt:
|
02/11/2022
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2022
| | | | |
|
Title:
|
IN-MEMORY ZERO VALUE DETECTION
|
|
|
Assignee
|
|
|
|
|
| 3003 TASMAN DRIVE |
| SANTA CLARA, CALIFORNIA 95054 |
|
|
Correspondence name and address
|
| |
DLA PIPER LLP (US)
|
| |
401 B STREET
|
| |
SUITE 1700
|
| |
SAN DIEGO, CA 92101
|
Search Results as of:
05/27/2024 01:28 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
| 
