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Reel/Frame:	019323/0528			Pages:	5
		Recorded:	05/16/2007
Attorney Dkt #:	SCS-550-1
Conveyance:	MERGER (SEE DOCUMENT FOR DETAILS).

Total properties: 64

Patent #:	5055716	Issue Dt:	10/08/1991	Application #:	07524183	Filing Dt:	05/15/1990
Title:	BASIC CELL FOR BICMOS GATE ARRAY

Patent #:	5289021	Issue Dt:	02/22/1994	Application #:	07717140	Filing Dt:	06/18/1991
Title:	BASIC CELL ARCHITECTURE FOR MASK PROGRAMMABLE GATE ARRAY WITH 3 OR MORE SIZE TRANSISTORS

Patent #:	5754826	Issue Dt:	05/19/1998	Application #:	08511172	Filing Dt:	08/04/1995
Title:	CAD AND SIMULATION SYSTEM FOR TARGETING IC DESIGNS TO MULTIPLE FABRICATION PROCESSES

Patent #:	6034908	Issue Dt:	03/07/2000	Application #:	08797347	Filing Dt:	02/11/1997
Title:	SENSE AMPLIFYING METHODS AND SENSE AMPLIFICATION INTEGRATED DEVICES

Patent #:	5717633	Issue Dt:	02/10/1998	Application #:	08798816	Filing Dt:	02/11/1997
Title:	LOW POWER CONSUMING MEMORY SENSE AMPLIFYING CIRCUITRY

Patent #:	5751649	Issue Dt:	05/12/1998	Application #:	08806335	Filing Dt:	02/26/1997
Title:	HIGH SPEED MEMORY OUTPUT CIRCUITRY AND METHODS FOR IMPLEMENTING SAME

Patent #:	6432726	Issue Dt:	08/13/2002	Application #:	08829772	Filing Dt:	03/31/1997
Publication #:	US20010046718	Pub Dt:	11/29/2001
Title:	METHOD AND APPARATUS FOR REDUCING PROCESS-INDUCED CHARGE BUILDUP

Patent #:	5886929	Issue Dt:	03/23/1999	Application #:	08837611	Filing Dt:	04/21/1997
Title:	HIGH SPEED ADDRESSING BUFFER AND METHODS FOR IMPLEMENTING SAME

Patent #:	5889715	Issue Dt:	03/30/1999	Application #:	08839151	Filing Dt:	04/23/1997
Title:	VOLTAGE SENSE AMPLIFIER AND METHODS FOR IMPLEMENTING THE SAME

Patent #:	5968192	Issue Dt:	10/19/1999	Application #:	08853276	Filing Dt:	05/09/1997
Title:	PROGRAMMABLE UNIVERSAL TEST INTERFACE AND METHOD FOR MAKING THE SAME

Patent #:	6177709	Issue Dt:	01/23/2001	Application #:	08885148	Filing Dt:	06/30/1997
Title:	CELL BASED ARRAY HAVING COMPUTE/DRIVE RATIOS OF N:1

Patent #:	5881008	Issue Dt:	03/09/1999	Application #:	08928713	Filing Dt:	09/12/1997
Title:	SELF ADJUSTING PRE-CHARGE DELAY IN MEMORY CIRCUITS AND METHODS FOR MAKING THE SAME

Patent #:	5883854	Issue Dt:	03/16/1999	Application #:	08928714	Filing Dt:	09/12/1997
Title:	DISTRIBUTED BALANCED ADDRESS DETECTION AND CLOCK BUFFER CIRCUITRY AND METHODS FOR MAKING THE SAME

Patent #:	5883834	Issue Dt:	03/16/1999	Application #:	08937561	Filing Dt:	09/25/1997
Title:	LOW POWER CONSUMING MEMORY SENSE AMPLIFYING CIRCUITRY

Patent #:	5965925	Issue Dt:	10/12/1999	Application #:	08956203	Filing Dt:	10/22/1997
Title:	INTEGRATED CIRCUIT LAYOUT METHODS AND LAYOUT STRUCTURES

Patent #:	5999482	Issue Dt:	12/07/1999	Application #:	08956981	Filing Dt:	10/24/1997
Title:	HIGH SPEED MEMORY SELF-TIMING CIRCUITRY AND METHODS FOR IMPLEMENTING THE SAME

Patent #:	5981987	Issue Dt:	11/09/1999	Application #:	08984029	Filing Dt:	12/02/1997
Title:	POWER GROUND METALLIZATION ROUTING IN A SEMICONDUCTOR DEVICE

Patent #:	6016390	Issue Dt:	01/18/2000	Application #:	09015427	Filing Dt:	01/29/1998
Title:	METHOD AND APPARATUS FOR ELIMINATING BITLINE VOLTAGE OFFSETS IN MEMORY DEVICES

Patent #:	6044481	Issue Dt:	03/28/2000	Application #:	09099913	Filing Dt:	06/18/1998
Title:	PROGRAMMABLE UNIVERSAL TEST INTERFACE FOR TESTING MEMORIES WITH DIFFERENT TEST METHODOLOGIES

Patent #:	6448631	Issue Dt:	09/10/2002	Application #:	09159264	Filing Dt:	09/23/1998
Publication #:	US20010045571	Pub Dt:	11/29/2001
Title:	CELL ARCHITECTURE WITH LOCAL INTERCONNECT AND METHOD FOR MAKING SAME

Patent #:	6445049	Issue Dt:	09/03/2002	Application #:	09163890	Filing Dt:	09/30/1998
Title:	CELL BASED ARRAY COMPRISING LOGIC, TRANSFER AND DRIVE CELLS

Patent #:	6177691	Issue Dt:	01/23/2001	Application #:	09164000	Filing Dt:	09/30/1998
Title:	CELL BASED ARRAY HAVING COMPUTE DRIVE RATIOS OF N:1

Patent #:	6072730	Issue Dt:	06/06/2000	Application #:	09177859	Filing Dt:	10/23/1998
Title:	LOW POWER DIFFERENTIAL SIGNAL TRANSITION TECHNIQUES FOR USE IN MEMORY DEVICES

Patent #:	6292927	Issue Dt:	09/18/2001	Application #:	09207159	Filing Dt:	12/07/1998
Title:	REDUCTION OF PROCESS ANTENNA EFFECTS IN INTEGRATED CIRCUITS

Patent #:	6367059	Issue Dt:	04/02/2002	Application #:	09273580	Filing Dt:	03/23/1999
Title:	CARRY CHAIN STANDARD CELL WITH CHARGE SHARING REDUCTION ARCHITECTURE

Patent #:	6477695	Issue Dt:	11/05/2002	Application #:	09337999	Filing Dt:	06/22/1999
Title:	METHODS FOR DESIGNING STANDARD CELL TRANSISTOR STRUCTURES

Patent #:	6307222	Issue Dt:	10/23/2001	Application #:	09368074	Filing Dt:	08/03/1999
Title:	POWER/GROUND METALLIZATION ROUTING IN A SEMICONDUCTOR DEVICE

Patent #:	6470304	Issue Dt:	10/22/2002	Application #:	09442877	Filing Dt:	11/18/1999
Title:	METHOD AND APPARATUS FOR ELIMINATING BITLINE VOLTAGE OFFSETS IN MEMORY DEVICES

Patent #:	6222791	Issue Dt:	04/24/2001	Application #:	09594977	Filing Dt:	06/15/2000
Title:	Slew tolerant clock input buffer

Patent #:	6369619	Issue Dt:	04/09/2002	Application #:	09615959	Filing Dt:	07/14/2000
Title:	Voltage tolerant input/output circuit

Patent #:	6696852	Issue Dt:	02/24/2004	Application #:	09626264	Filing Dt:	07/25/2000
Title:	LOW-VOLTAGE DIFFERENTIAL I/O DEVICE

Patent #:	6542396	Issue Dt:	04/01/2003	Application #:	09675574	Filing Dt:	09/29/2000
Title:	METHOD AND APPARATUS FOR A DENSE METAL PROGRAMMABLE ROM

Patent #:	6446250	Issue Dt:	09/03/2002	Application #:	09678433	Filing Dt:	10/02/2000
Title:	INPUT/OUTPUT CELL GENERATOR

Patent #:	6550047	Issue Dt:	04/15/2003	Application #:	09679059	Filing Dt:	10/02/2000
Title:	SEMICONDUCTOR CHIP INPUT/OUTPUT CELL DESIGN AND AUTOMATED GENERATION METHODS

Patent #:	6594813	Issue Dt:	07/15/2003	Application #:	09703975	Filing Dt:	10/31/2000
Title:	CELL ARCHITECTURE WITH LOCAL INTERCONNECT AND METHOD FOR MAKING SAME

Patent #:	6640330	Issue Dt:	10/28/2003	Application #:	09841797	Filing Dt:	04/24/2001
Title:	SYSTEM AND METHOD FOR SETUP AND HOLD CHARACTERIZATION IN INTEGRATED CIRCUIT CELLS

Patent #:	6569714	Issue Dt:	05/24/2010	Application #:	09896055	Filing Dt:	06/28/2001
Publication #:	US20020039812	Pub Dt:	04/04/2002
Title:	METHOD AND APPARATUS FOR A DENSE METAL PROGRAMMABLE ROM

Patent #:	6525954	Issue Dt:	02/25/2003	Application #:	09896444	Filing Dt:	06/28/2001
Publication #:	US20020039305	Pub Dt:	04/04/2002
Title:	METHOD AND APPARATUS FOR A DENSE METAL PROGRAMMABLE ROM

Patent #:	6570195	Issue Dt:	05/27/2003	Application #:	09929320	Filing Dt:	08/13/2001
Publication #:	US20010054720	Pub Dt:	12/27/2001
Title:	POWER/GROUND METALLIZATION ROUTING IN A SEMICONDUCTOR DEVICE

Patent #:	6731135	Issue Dt:	05/04/2004	Application #:	09991107	Filing Dt:	11/16/2001
Publication #:	US20020190754	Pub Dt:	12/19/2002
Title:	LOW VOLTAGE DIFFERENTIAL SIGNALING CIRCUIT WITH MID-POINT BIAS

Patent #:	6915251	Issue Dt:	07/05/2005	Application #:	10026245	Filing Dt:	12/17/2001
Publication #:	US20020056071	Pub Dt:	05/09/2002
Title:	MEMORIES HAVING REDUCED BITLINE VOLTAGE OFFSETS

Patent #:	6944582	Issue Dt:	09/13/2005	Application #:	10026246	Filing Dt:	12/17/2001
Publication #:	US20020056072	Pub Dt:	05/09/2002
Title:	METHODS FOR REDUCING BITLINE VOLTAGE OFFSETS IN MEMORY DEVICES

Patent #:	6973605	Issue Dt:	12/06/2005	Application #:	10074517	Filing Dt:	02/12/2002
Title:	SYSTEM AND METHOD FOR ASSURED BUILT IN SELF REPAIR OF MEMORIES

Patent #:	6618311	Issue Dt:	09/09/2003	Application #:	10074559	Filing Dt:	02/12/2002
Title:	ZERO POWER FUSE SENSING CIRCUIT FOR REDUNDANCY APPLICATIONS IN MEMORIES

Patent #:	6667917	Issue Dt:	12/23/2003	Application #:	10077837	Filing Dt:	02/15/2002
Publication #:	US20040004872	Pub Dt:	01/08/2004
Title:	SYSTEM AND METHOD FOR IDENTIFICATION OF FAULTY OR WEAK MEMORY CELLS UNDER SIMULATED EXTREME OPERATING CONDITIONS

Patent #:	6597613	Issue Dt:	07/22/2003	Application #:	10113759	Filing Dt:	03/27/2002
Title:	LOAD INDEPENDENT SINGLE ENDED SENSE AMPLIFIER

Patent #:	6750712	Issue Dt:	06/15/2004	Application #:	10170526	Filing Dt:	06/12/2002
Title:	METHOD AND APPARATUS FOR VOLTAGE CLAMPING IN FEEDBACK AMPLIFIERS USING RESISTORS

Patent #:	6617925	Issue Dt:	09/09/2003	Application #:	10172206	Filing Dt:	06/13/2002
Publication #:	US20020190795	Pub Dt:	12/19/2002
Title:	METHOD AND APPARATUS FOR GAIN COMPENSATION AND CONTROL IN LOW VOLTAGE DIFFERENTIAL SIGNALING APPLICATIONS

Patent #:	6966012	Issue Dt:	11/15/2005	Application #:	10179773	Filing Dt:	06/24/2002
Title:	MEMORY COLUMN REDUNDANCY CIRCUITRY AND METHOD FOR IMPLEMENTING THE SAME

Patent #:	6639286	Issue Dt:	10/28/2003	Application #:	10191931	Filing Dt:	07/08/2002
Publication #:	US20030027399	Pub Dt:	02/06/2003
Title:	METHOD AND APPARATUS FOR REDUCING PROCESS-INDUCED CHARGE BUILDUP

Patent #:	6674661	Issue Dt:	01/06/2004	Application #:	10350497	Filing Dt:	01/23/2003
Title:	METHOD AND APPARATUS FOR A DENSE METAL PROGRAMMABLE ROM

Patent #:	6833624	Issue Dt:	12/21/2004	Application #:	10364198	Filing Dt:	02/10/2003
Publication #:	US20040155343	Pub Dt:	08/12/2004
Title:	SYSTEM AND METHOD FOR ROW DECODE IN A MULTIPORT MEMORY

Patent #:	6865119	Issue Dt:	03/08/2005	Application #:	10364719	Filing Dt:	02/10/2003
Publication #:	US20040156244	Pub Dt:	08/12/2004
Title:	NEGATIVELY CHARGED WORDLINE FOR REDUCED SUBTHRESHOLD CURRENT

Patent #:	6788615	Issue Dt:	09/07/2004	Application #:	10364720	Filing Dt:	02/10/2003
Publication #:	US20040156261	Pub Dt:	08/12/2004
Title:	SYSTEM AND METHOD FOR LOW AREA SELF-TIMING IN MEMORY DEVICES

Patent #:	6941525	Issue Dt:	09/06/2005	Application #:	10448636	Filing Dt:	05/29/2003
Publication #:	US20040243946	Pub Dt:	12/02/2004
Title:	LEAKAGE CURRENT REDUCTION IN STANDARD CELLS

Patent #:	6934213	Issue Dt:	08/23/2005	Application #:	10460626	Filing Dt:	06/11/2003
Publication #:	US20040252572	Pub Dt:	12/16/2004
Title:	METHOD AND APPARATUS FOR REDUCING WRITE POWER CONSUMPTION IN RANDOM ACCESS MEMORIES

Patent #:	6924687	Issue Dt:	08/02/2005	Application #:	10630949	Filing Dt:	07/29/2003
Publication #:	US20050024101	Pub Dt:	02/03/2005
Title:	VOLTAGE TOLERANT CIRCUIT FOR PROTECTING AN INPUT BUFFER

Patent #:	6862721	Issue Dt:	03/01/2005	Application #:	10665862	Filing Dt:	09/17/2003
Publication #:	US20040062095	Pub Dt:	04/01/2004
Title:	METHOD FOR IDENTIFICATION OF FAULTY OR WEAK FUNCTIONAL LOGIC ELEMENTS UNDER SIMULATED EXTREME OPERATING CONDITIONS

Patent #:	6957402	Issue Dt:	10/18/2005	Application #:	10671029	Filing Dt:	09/24/2003
Publication #:	US20050066294	Pub Dt:	03/24/2005
Title:	YIELD MAXIMIZATION IN THE MANUFACTURE OF INTEGRATED CIRCUITS

Patent #:	7002258	Issue Dt:	02/21/2006	Application #:	10727760	Filing Dt:	12/03/2003
Publication #:	US20050121810	Pub Dt:	06/09/2005
Title:	DUAL PORT MEMORY CORE CELL ARCHITECTURE WITH MATCHED BIT LINE CAPACITANCES

Patent #:	7005910	Issue Dt:	02/28/2006	Application #:	10759339	Filing Dt:	01/16/2004
Publication #:	US20050156642	Pub Dt:	07/21/2005
Title:	FEED-FORWARD CIRCUIT FOR REDUCING DELAY THROUGH AN INPUT BUFFER

Patent #:	7005913	Issue Dt:	02/28/2006	Application #:	10807419	Filing Dt:	03/22/2004
Publication #:	US20050068070	Pub Dt:	03/31/2005
Title:	I/O BUFFER WITH WIDE RANGE VOLTAGE TRANSLATOR

Patent #:	6999354	Issue Dt:	02/14/2006	Application #:	10833388	Filing Dt:	04/27/2004
Publication #:	US20050237823	Pub Dt:	10/27/2005
Title:	DYNAMICALLY ADAPTABLE MEMORY

Patent #:	8106463	Issue Dt:	01/31/2012	Application #:	11296029	Filing Dt:	12/06/2005
Publication #:	US20070126049	Pub Dt:	06/07/2007
Title:	MEMORY CELLS FOR READ ONLY MEMORIES

Assignor

ARM PHYSICAL IP, INC.

Exec Dt:

12/18/2006

Assignee

ARM, INC.

141 CASPIAN COURT

SUNNYVALE, CALIFORNIA 94089-1013

Correspondence name and address
	STANLEY C. SPOONER
	NIXON & VANDERHYE P.C.
	901 NORTH GLEBE ROAD
	11TH FLOOR
	ARLINGTON, VA 22203

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