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Patent Assignment Details
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Reel/Frame:016298/0530   Pages: 5
Recorded: 02/22/2005
Conveyance: RESUBMITTED TO CORRECT SPELLING OF INVENTOR NAME JEFFREY C. DILLON
Total properties: 1
1
Patent #:
Issue Dt:
02/23/2010
Application #:
10746284
Filing Dt:
12/23/2003
Publication #:
Pub Dt:
12/16/2004
Title:
SYNTHESIS OF VERTICAL BLANKING SIGNAL
Assignors
1
Exec Dt:
06/07/2004
2
Exec Dt:
03/11/2004
3
Exec Dt:
04/30/2004
4
Exec Dt:
03/11/2004
5
Exec Dt:
03/12/2004
6
Exec Dt:
06/03/2004
Assignee
1
1 INFINITE LOOP
CUPERTINO, CALIFORNIA 95014
Correspondence name and address
SIERRA PATENT GROUP, LTD.
P.O. BOX 6149
STATELINE, NV 89449

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