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Total properties:
17
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Patent #:
|
|
Issue Dt:
|
09/12/1995
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Application #:
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08142648
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Filing Dt:
|
10/25/1993
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Title:
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VLIW PROCESSOR WHICH USES PATH INFORMATION GENERATED BY A BRANCH CONTROL UNIT TO INHIBIT OPERATIONS WHICH ARE NOT ON A CORRECT PATH
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Patent #:
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|
Issue Dt:
|
11/03/1998
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Application #:
|
08358127
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Filing Dt:
|
12/16/1994
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Title:
|
EXCEPTION RECOVERY IN A DATA PROCESSING SYSTEM
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Patent #:
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|
Issue Dt:
|
04/09/2002
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Application #:
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08366958
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Filing Dt:
|
12/30/1994
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Title:
|
MULTIPORT REGISTER FILE TO ACCOMMODATE DATA OF DIFFERING LENGTHS
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Patent #:
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|
Issue Dt:
|
11/25/1997
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Application #:
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08425697
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Filing Dt:
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04/19/1995
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Title:
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VLIW PROCESSING DEVICE INCLUDING IMPROVED MEMORY FOR AVOIDING COLLISIONS WITHOUT AN EXCESSIVE NUMBER OF PORTS
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Patent #:
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|
Issue Dt:
|
10/10/2000
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Application #:
|
08648333
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Filing Dt:
|
05/15/1996
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Title:
|
PLANAR CACHE LAYOUT AND INSTRUCTION STREAM THEREFOR
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|
|
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Patent #:
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|
Issue Dt:
|
08/18/2009
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Application #:
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09794943
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Filing Dt:
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02/28/2001
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Publication #:
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Pub Dt:
|
09/06/2001
| | | | |
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Title:
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DATA PROCESSOR WITH MULTI-COMMAND INSTRUCTION WORDS
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|
|
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Patent #:
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|
Issue Dt:
|
04/26/2005
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Application #:
|
09895473
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Filing Dt:
|
06/29/2001
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Title:
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Replacing VLIW operation with equivalent operation requiring fewer issue slots
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|
|
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Patent #:
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|
Issue Dt:
|
01/29/2013
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Application #:
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10530495
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Filing Dt:
|
04/06/2005
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|
Publication #:
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|
Pub Dt:
|
01/05/2006
| | | | |
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Title:
|
DATA PROCESSING APPARATUS ADDRESS RANGE DEPENDENT PARALLELIZATION OF INSTRUCTIONS
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|
|
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Patent #:
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|
Issue Dt:
|
03/30/2010
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Application #:
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10552777
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Filing Dt:
|
10/12/2005
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|
Publication #:
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Pub Dt:
|
03/22/2007
| | | | |
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Title:
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PROCESSING OF A COMPILEABLE COMPUTER PROGRAM
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|
|
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Patent #:
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|
Issue Dt:
|
11/02/2010
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Application #:
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10570290
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Filing Dt:
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02/28/2006
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Publication #:
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Pub Dt:
|
01/04/2007
| | | | |
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Title:
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INTERGRATED CIRCUIT AND A METHOD OF CACHE REMAPPING
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|
|
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Patent #:
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|
Issue Dt:
|
05/11/2010
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Application #:
|
10583052
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Filing Dt:
|
06/14/2006
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|
Publication #:
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Pub Dt:
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07/12/2007
| | | | |
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Title:
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MEMORY-EFFICIENT INSTRUCTION PROCESSING SCHEME
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|
|
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Patent #:
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|
Issue Dt:
|
09/17/2013
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Application #:
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11814801
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Filing Dt:
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03/25/2008
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Publication #:
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Pub Dt:
|
08/14/2008
| | | | |
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Title:
|
ALLOCATING REGISTERS FOR LOOP VARIABLES IN A MULTI-THREADED PROCESSOR
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|
|
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|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11916328
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Filing Dt:
|
06/22/2010
|
|
Publication #:
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|
Pub Dt:
|
10/14/2010
| | | | |
|
Title:
|
DATA PROCESSING SYSTEM AND METHOD FOR SCHEDULING THE USE OF AT LEAST ONE EXCLUSIVE RESOURCE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
06/03/2014
|
Application #:
|
12090028
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Filing Dt:
|
12/30/2008
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|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
|
Title:
|
PROGRAM EXECUTABLE IMAGE ENCRYPTION
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12306605
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Filing Dt:
|
12/24/2008
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|
Publication #:
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|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
DECODING SOUND PARAMETERS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
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Application #:
|
12673898
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Filing Dt:
|
02/17/2010
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|
Publication #:
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|
Pub Dt:
|
03/24/2011
| | | | |
|
Title:
|
DATA PROCESSING WITH PROTECTION AGAINST SOFT ERRORS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
05/20/2014
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Application #:
|
12682789
|
Filing Dt:
|
08/09/2010
|
|
Publication #:
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Pub Dt:
|
11/25/2010
| | | | |
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Title:
|
CIRCUIT AND METHOD WITH CACHE COHERENCE STRESS CONTROL
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