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Total properties:
20
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Patent #:
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|
Issue Dt:
|
09/29/1998
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Application #:
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08496630
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Filing Dt:
|
06/29/1995
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Title:
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COMPUTER METHOD AND APPARATUS WHICH MAINTAINS CONTEXT SWITCHING SPEED WITH A LARGE NUMBER OF REGISTERS AND WHICH IMPROVES INTERRUPT PROCESSING TIME
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Patent #:
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Issue Dt:
|
01/19/1999
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Application #:
|
08649732
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Filing Dt:
|
05/15/1996
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Title:
|
COMPILER GENERATING SWIZZLED INSTRUCTIONS USABLE IN A SIMPLIFIED CACHE LAYOUT
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Patent #:
|
|
Issue Dt:
|
11/02/1999
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Application #:
|
09009751
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Filing Dt:
|
01/20/1998
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Title:
|
PERFORMING PENDING INTERRUPTS OR EXCEPTIONS WHEN INTERRUPTIBLE JUMPS ARE DETECTED
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|
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Patent #:
|
|
Issue Dt:
|
11/04/2003
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Application #:
|
09805384
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Filing Dt:
|
03/13/2001
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Publication #:
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Pub Dt:
|
09/19/2002
| | | | |
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Title:
|
CACHE WAY PREDICTION BASED ON INSTRUCTION BASE REGISTER
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Patent #:
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|
Issue Dt:
|
07/18/2006
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Application #:
|
09868797
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Filing Dt:
|
09/25/2001
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Title:
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DEVICE AND METHOD FOR GENERATING AND EXECUTING COMPRESSED PROGRAMS OF A VERY LONG INSTRUCTION WORD PROCESSOR
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Patent #:
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Issue Dt:
|
01/13/2004
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Application #:
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09887463
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Filing Dt:
|
06/22/2001
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Publication #:
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Pub Dt:
|
01/16/2003
| | | | |
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Title:
|
FAST AND ACCURATE CACHE WAY SELECTION
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|
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Patent #:
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|
Issue Dt:
|
07/06/2004
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Application #:
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10136732
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Filing Dt:
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05/01/2002
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Publication #:
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Pub Dt:
|
11/06/2003
| | | | |
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Title:
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MEMORY REGION BASED DATA PRE-FETCHING
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Patent #:
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Issue Dt:
|
07/29/2008
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Application #:
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10218074
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Filing Dt:
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08/12/2002
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Publication #:
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Pub Dt:
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02/12/2004
| | | | |
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Title:
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INSTRUCTION CACHE WAY PREDICTION FOR JUMP TARGETS
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Patent #:
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Issue Dt:
|
01/09/2007
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Application #:
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10226158
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Filing Dt:
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08/23/2002
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Publication #:
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Pub Dt:
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02/26/2004
| | | | |
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Title:
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PROCESSOR PREFETCH TO MATCH MEMORY BUS PROTOCOL CHARACTERISTICS
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Patent #:
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Issue Dt:
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12/30/2008
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Application #:
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10496537
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Filing Dt:
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05/24/2004
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Publication #:
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Pub Dt:
|
12/30/2004
| | | | |
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Title:
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REROUTING VLIW INSTRUCTIONS TO ACCOMMODATE EXECUTION UNITS DEACTIVATED UPON DETECTION BY DISPATCH UNITS OF DEDICATED INSTRUCTION ALERTING MULTIPLE SUCCESSIVE REMOVED NOPS
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Patent #:
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Issue Dt:
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01/10/2012
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Application #:
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10511512
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Filing Dt:
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10/14/2004
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Publication #:
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Pub Dt:
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06/16/2005
| | | | |
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Title:
|
REGISTER SYSTEMS AND METHODS FOR A MULTI-ISSUE PROCESSOR
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
|
10535591
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Filing Dt:
|
05/19/2005
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Publication #:
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Pub Dt:
|
03/16/2006
| | | | |
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Title:
|
Using a cache miss pattern to address a stride prediction table
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|
|
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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11719399
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Filing Dt:
|
05/11/2009
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Publication #:
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Pub Dt:
|
08/27/2009
| | | | |
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Title:
|
CACHE WITH PREFETCH
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|
|
|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11994245
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Filing Dt:
|
10/24/2008
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Publication #:
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Pub Dt:
|
07/02/2009
| | | | |
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Title:
|
MULTI-PHASE FREQUENCY DIVIDER
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|
|
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Patent #:
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|
Issue Dt:
|
07/17/2012
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Application #:
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11995091
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Filing Dt:
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10/31/2008
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Publication #:
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Pub Dt:
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08/20/2009
| | | | |
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Title:
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USING HISTORIC LOAD PROFILES TO DYNAMICALLY ADJUST OPERATING FREQUENCY AND AVAILABLE POWER TO A HANDHELD MULTIMEDIA DEVICE PROCESSOR CORE
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|
|
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Patent #:
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|
Issue Dt:
|
07/05/2011
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Application #:
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12090689
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Filing Dt:
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04/18/2008
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Publication #:
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Pub Dt:
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08/28/2008
| | | | |
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Title:
|
CACHE WITH HIGH ACCESS STORE BANDWIDTH
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|
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Patent #:
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|
Issue Dt:
|
02/17/2015
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Application #:
|
12518485
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Filing Dt:
|
06/10/2009
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|
Publication #:
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Pub Dt:
|
02/25/2010
| | | | |
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Title:
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PIPELINED PROCESSOR AND COMPILER/SCHEDULER FOR VARIABLE NUMBER BRANCH DELAY SLOTS
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|
|
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|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
12518500
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Filing Dt:
|
06/10/2009
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|
Publication #:
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Pub Dt:
|
01/07/2010
| | | | |
|
Title:
|
VIRTUAL FUNCTIONAL UNITS FOR VLIW PROCESSORS
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|
|
|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
12523388
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Filing Dt:
|
07/16/2009
|
|
Publication #:
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Pub Dt:
|
03/25/2010
| | | | |
|
Title:
|
HARDWARE TRIGGERED DATA CACHE LINE PRE-ALLOCATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2012
|
Application #:
|
12531726
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Filing Dt:
|
09/17/2009
|
|
Publication #:
|
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Pub Dt:
|
04/08/2010
| | | | |
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Title:
|
ELECTRONIC DEVICE AND METHOD DETERMINING A WORKLOAD OF AN ELECTRONIC DEVICE
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|
