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Patent Assignment Details
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Reel/Frame:013966/0543   Pages: 3
Recorded: 04/11/2003
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
NONE
Issue Dt:
Application #:
10411892
Filing Dt:
04/11/2003
Publication #:
Pub Dt:
11/27/2003
Title:
Planarized semiconductor interconnect topography and method for polishing a metal layer to form wide interconnect structures
Assignors
1
Exec Dt:
10/28/1998
2
Exec Dt:
10/28/1998
3
Exec Dt:
10/28/1998
Assignee
1
3901 N. FIRST STREET
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
CONLEY ROSE, P.C.
KEVIN L. JAFFER
P.O. BOX 684908
AUSTIN, TX 78768-4908

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