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Reel/Frame:057261/0545   Pages: 7
Recorded: 06/18/2021
Attorney Dkt #:VARIOUS
Conveyance: MERGER AND CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 98
1
Patent #:
7831941
Issue Dt:
11/09/2010
Application #:
11968458
Filing Dt:
01/02/2008
Publication #:
US20090171644
Pub Dt:
07/02/2009
Title:
CA RESISTANCE VARIABILITY PREDICTION METHODOLOGY
2
Patent #:
7844928
Issue Dt:
11/30/2010
Application #:
11972747
Filing Dt:
01/11/2008
Publication #:
US20090183127
Pub Dt:
07/16/2009
Title:
METHOD AND APPARATUS FOR EVALUATING INTEGRATED CIRCUIT DESIGN PERFORMANCE USING ENHANCED BASIC BLOCK VECTORS THAT INCLUDE DATA DEPENDENT INFORMATION
3
Patent #:
7870515
Issue Dt:
01/11/2011
Application #:
11972923
Filing Dt:
01/11/2008
Publication #:
US20090183130
Pub Dt:
07/16/2009
Title:
SYSTEM AND METHOD FOR IMPROVED HIERARCHICAL ANALYSIS OF ELECTRONIC CIRCUITS
4
Patent #:
7873925
Issue Dt:
01/18/2011
Application #:
12013925
Filing Dt:
01/14/2008
Publication #:
US20090182522
Pub Dt:
07/16/2009
Title:
METHOD AND APPARATUS FOR COMPUTING TEST MARGINS FOR AT-SPEED TESTING
5
Patent #:
8073288
Issue Dt:
12/06/2011
Application #:
12015084
Filing Dt:
01/16/2008
Publication #:
US20090180711
Pub Dt:
07/16/2009
Title:
RENDERING A MASK USING COARSE MASK REPRESENTATION
6
Patent #:
7904865
Issue Dt:
03/08/2011
Application #:
12018422
Filing Dt:
01/23/2008
Publication #:
US20090187870
Pub Dt:
07/23/2009
Title:
PLACEMENT DRIVEN ROUTING
7
Patent #:
7849427
Issue Dt:
12/07/2010
Application #:
12021363
Filing Dt:
01/29/2008
Publication #:
US20090193383
Pub Dt:
07/30/2009
Title:
AUTO-ROUTER PERFORMING SIMULTANEOUS PLACEMENT OF SIGNAL AND RETURN PATHS
8
Patent #:
8020129
Issue Dt:
09/13/2011
Application #:
12021723
Filing Dt:
01/29/2008
Publication #:
US20090193373
Pub Dt:
07/30/2009
Title:
MULTIPLE VOLTAGE THRESHOLD TIMING ANALYSIS FOR A DIGITAL INTEGRATED CIRCUIT
9
Patent #:
8140313
Issue Dt:
03/20/2012
Application #:
12022309
Filing Dt:
01/30/2008
Publication #:
US20090193390
Pub Dt:
07/30/2009
Title:
TECHNIQUES FOR MODELING VARIABLES IN SUBPROGRAMS OF HARDWARE DESCRIPTION LANGUAGE PROGRAMS
10
Patent #:
7770140
Issue Dt:
08/03/2010
Application #:
12026141
Filing Dt:
02/05/2008
Publication #:
US20090199138
Pub Dt:
08/06/2009
Title:
METHOD AND APPARATUS FOR EVALUATING INTEGRATED CIRCUIT DESIGN MODEL PERFORMANCE USING BASIC BLOCK VECTORS AND FLY-BY VECTORS INCLUDING MICROARCHITECTURE DEPENDENT INFORMATION
11
Patent #:
7945887
Issue Dt:
05/17/2011
Application #:
12028854
Filing Dt:
02/11/2008
Publication #:
US20090204365
Pub Dt:
08/13/2009
Title:
MODELING SPATIAL CORRELATIONS
12
Patent #:
7844418
Issue Dt:
11/30/2010
Application #:
12030462
Filing Dt:
02/13/2008
Publication #:
US20090204367
Pub Dt:
08/13/2009
Title:
METHODS FOR DISTRIBUTING A RANDOM VARIABLE USING STATISTICALLY-CORRECT SPATIAL INTERPOLATION
13
Patent #:
7908532
Issue Dt:
03/15/2011
Application #:
12032655
Filing Dt:
02/16/2008
Publication #:
US20090210763
Pub Dt:
08/20/2009
Title:
AUTOMATED SYSTEM AND PROCESSING FOR EXPEDIENT DIAGNOSIS OF BROKEN SHIFT REGISTERS LATCH CHAINS
14
Patent #:
7904847
Issue Dt:
03/08/2011
Application #:
12032745
Filing Dt:
02/18/2008
Publication #:
US20090210831
Pub Dt:
08/20/2009
Title:
CMOS CIRCUIT LEAKAGE CURRENT CALCULATOR
15
Patent #:
7921399
Issue Dt:
04/05/2011
Application #:
12032823
Filing Dt:
02/18/2008
Publication #:
US20090210850
Pub Dt:
08/20/2009
Title:
METHOD FOR SIMPLIFYING TIE NET MODELING FOR ROUTER PERFORMANCE
16
Patent #:
7831879
Issue Dt:
11/09/2010
Application #:
12033239
Filing Dt:
02/19/2008
Publication #:
US20090210746
Pub Dt:
08/20/2009
Title:
GENERATING TEST COVERAGE BIN BASED ON SIMULATION RESULT
17
Patent #:
7409662
Issue Dt:
08/05/2008
Application #:
12033668
Filing Dt:
02/19/2008
Title:
SYSTEMS AND METHODS INVOLVING DESIGNING SHIELDING PROFILES FOR INTEGRATED CIRCUITS
18
Patent #:
8024597
Issue Dt:
09/20/2011
Application #:
12034896
Filing Dt:
02/21/2008
Publication #:
US20090217075
Pub Dt:
08/27/2009
Title:
SIGNAL PHASE VERIFICATION FOR SYSTEMS INCORPORATING TWO SYNCHRONOUS CLOCK DOMAINS
19
Patent #:
7962880
Issue Dt:
06/14/2011
Application #:
12035506
Filing Dt:
02/22/2008
Publication #:
US20090217229
Pub Dt:
08/27/2009
Title:
WIRE STRUCTURES MINIMIZING COUPLING EFFECTS BETWEEN WIRES IN A BUS
20
Patent #:
7941775
Issue Dt:
05/10/2011
Application #:
12044223
Filing Dt:
03/07/2008
Publication #:
US20090228851
Pub Dt:
09/10/2009
Title:
ARBITRARY WAVEFORM PROPAGATION THROUGH A LOGIC GATE USING TIMING ANALYSIS RESULTS
21
Patent #:
7844932
Issue Dt:
11/30/2010
Application #:
12045915
Filing Dt:
03/11/2008
Publication #:
US20090235217
Pub Dt:
09/17/2009
Title:
METHOD TO IDENTIFY TIMING VIOLATIONS OUTSIDE OF MANUFACTURING SPECIFICATION LIMITS
22
Patent #:
7971176
Issue Dt:
06/28/2011
Application #:
12050207
Filing Dt:
03/18/2008
Publication #:
US20090240458
Pub Dt:
09/24/2009
Title:
METHOD FOR TESTING INTEGRATED CIRCUITS
23
Patent #:
7784000
Issue Dt:
08/24/2010
Application #:
12050381
Filing Dt:
03/18/2008
Publication #:
US20090240459
Pub Dt:
09/24/2009
Title:
IDENTIFYING SEQUENTIAL FUNCTIONAL PATHS FOR IC TESTING METHODS AND SYSTEM
24
Patent #:
8095837
Issue Dt:
01/10/2012
Application #:
12051744
Filing Dt:
03/19/2008
Publication #:
US20090240995
Pub Dt:
09/24/2009
Title:
METHOD AND APPARATUS FOR IMPROVING RANDOM PATTERN TESTING OF LOGIC STRUCTURES
25
Patent #:
7849429
Issue Dt:
12/07/2010
Application #:
12053887
Filing Dt:
03/24/2008
Publication #:
US20090241078
Pub Dt:
09/24/2009
Title:
METHODS FOR CONSERVING MEMORY IN STATISTICAL STATIC TIMING ANALYSIS
26
Patent #:
7836418
Issue Dt:
11/16/2010
Application #:
12053923
Filing Dt:
03/24/2008
Publication #:
US20090241079
Pub Dt:
09/24/2009
Title:
METHOD AND SYSTEM FOR ACHIEVING POWER OPTIMIZATION IN A HIERARCHICAL NETLIST
27
Patent #:
7873926
Issue Dt:
01/18/2011
Application #:
12059015
Filing Dt:
03/31/2008
Publication #:
US20090249270
Pub Dt:
10/01/2009
Title:
METHODS FOR PRACTICAL WORST TEST DEFINITION AND DEBUG DURING BLOCK BASED STATISTICAL STATIC TIMING ANALYSIS
28
Patent #:
7523433
Issue Dt:
04/21/2009
Application #:
12059703
Filing Dt:
03/31/2008
Title:
SYSTEM AND METHOD FOR AUTOMATED ANALYSIS AND HIERARCHICAL GRAPHICAL PRESENTATION OF APPLICATION RESULTS
29
Patent #:
7856582
Issue Dt:
12/21/2010
Application #:
12061752
Filing Dt:
04/03/2008
Publication #:
US20090254788
Pub Dt:
10/08/2009
Title:
TECHNIQUES FOR LOGIC BUILT-IN SELF-TEST DIAGNOSTICS OF INTEGRATED CIRCUIT DEVICES
30
Patent #:
7895557
Issue Dt:
02/22/2011
Application #:
12100477
Filing Dt:
04/10/2008
Publication #:
US20090259980
Pub Dt:
10/15/2009
Title:
METHOD AND SYSTEM FOR CONCURRENT BUFFERING AND LAYER ASSIGNMENT IN INTEGRATED CIRCUIT LAYOUT
31
Patent #:
7895545
Issue Dt:
02/22/2011
Application #:
12103217
Filing Dt:
04/15/2008
Publication #:
US20090259983
Pub Dt:
10/15/2009
Title:
METHODS FOR DESIGNING A PRODUCT CHIP A PRIORI FOR DESIGN SUBSETTING, FEATURE ANALYSIS, AND YIELD LEARNING
32
Patent #:
7886246
Issue Dt:
02/08/2011
Application #:
12103845
Filing Dt:
04/16/2008
Publication #:
US20090265674
Pub Dt:
10/22/2009
Title:
METHODS FOR IDENTIFYING FAILING TIMING REQUIREMENTS IN A DIGITAL DESIGN
33
Patent #:
7941780
Issue Dt:
05/10/2011
Application #:
12105299
Filing Dt:
04/18/2008
Publication #:
US20090265673
Pub Dt:
10/22/2009
Title:
INTERSECT AREA BASED GROUND RULE FOR SEMICONDUCTOR DESIGN
34
Patent #:
7865854
Issue Dt:
01/04/2011
Application #:
12108145
Filing Dt:
04/23/2008
Publication #:
US20090271165
Pub Dt:
10/29/2009
Title:
SIMULTANEOUS PARAMETER-DRIVEN AND DETERMINISTIC SIMULATION WITH OR WITHOUT SYNCHRONIZATION
35
Patent #:
7934188
Issue Dt:
04/26/2011
Application #:
12108599
Filing Dt:
04/24/2008
Publication #:
US20090271752
Pub Dt:
10/29/2009
Title:
LEGALIZATION OF VLSI CIRCUIT PLACEMENT WITH BLOCKAGES USING HIERARCHICAL ROW SLICING
36
Patent #:
7844938
Issue Dt:
11/30/2010
Application #:
12109400
Filing Dt:
04/25/2008
Publication #:
US20090271757
Pub Dt:
10/29/2009
Title:
DATA CORRECTING HIERARCHICAL INTEGRATED CIRCUIT LAYOUT ACCOMMODATING COMPENSATE FOR LONG RANGE CRITICAL DIMENSION VARIATION
37
Patent #:
7882454
Issue Dt:
02/01/2011
Application #:
12110731
Filing Dt:
04/28/2008
Publication #:
US20090271671
Pub Dt:
10/29/2009
Title:
APPARATUS AND METHOD FOR IMPROVED TEST CONTROLLABILITY AND OBSERVABILITY OF RANDOM RESISTANT LOGIC
38
Patent #:
7882460
Issue Dt:
02/01/2011
Application #:
12111574
Filing Dt:
04/29/2008
Publication #:
US20090271746
Pub Dt:
10/29/2009
Title:
METHOD OF CIRCUIT POWER TUNING THROUGH POST-PROCESS FLATTENING
39
Patent #:
7886247
Issue Dt:
02/08/2011
Application #:
12111634
Filing Dt:
04/29/2008
Publication #:
US20090271751
Pub Dt:
10/29/2009
Title:
METHOD AND APPARATUS FOR STATISTICAL PATH SELECTION FOR AT-SPEED TESTING
40
Patent #:
7904870
Issue Dt:
03/08/2011
Application #:
12112035
Filing Dt:
04/30/2008
Publication #:
US20090276191
Pub Dt:
11/05/2009
Title:
METHOD AND APPARATUS FOR INTEGRATED CIRCUIT DESIGN MODEL PERFORMANCE EVALUATION USING BASIC BLOCK VECTOR CLUSTERING AND FLY-BY VECTOR CLUSTERING
41
Patent #:
7503023
Issue Dt:
03/10/2009
Application #:
12112529
Filing Dt:
04/30/2008
Title:
EFFICIENT METHOD FOR LOCATING A SHORT CIRCUIT
42
Patent #:
7865793
Issue Dt:
01/04/2011
Application #:
12113116
Filing Dt:
04/30/2008
Publication #:
US20090276610
Pub Dt:
11/05/2009
Title:
TEST CASE GENERATION WITH BACKWARD PROPAGATION OF PREDEFINED RESULTS AND OPERAND DEPENDENCIES
43
Patent #:
7890906
Issue Dt:
02/15/2011
Application #:
12117761
Filing Dt:
05/09/2008
Publication #:
US20090282380
Pub Dt:
11/12/2009
Title:
METHOD OF LAYING OUT INTEGRATED CIRCUIT DESIGN BASED ON KNOWN POLYSILICON PERIMETER DENSITIES OF INDIVIDUAL CELLS
44
Patent #:
7849433
Issue Dt:
12/07/2010
Application #:
12117771
Filing Dt:
05/09/2008
Publication #:
US20090278222
Pub Dt:
11/12/2009
Title:
INTEGRATED CIRCUIT WITH UNIFORM POLYSILICON PERIMETER DENSITY, METHOD AND DESIGN STRUCTURE
45
Patent #:
8086976
Issue Dt:
12/27/2011
Application #:
12121023
Filing Dt:
05/15/2008
Publication #:
US20090288051
Pub Dt:
11/19/2009
Title:
METHODS FOR STATISTICAL SLEW PROPAGATION DURING BLOCK-BASED STATISTICAL STATIC TIMING ANALYSIS
46
Patent #:
7971171
Issue Dt:
06/28/2011
Application #:
12123769
Filing Dt:
05/20/2008
Publication #:
US20090013290
Pub Dt:
01/08/2009
Title:
METHOD AND SYSTEM FOR ELECTROMIGRATION ANALYSIS ON SIGNAL WIRING
47
Patent #:
7530041
Issue Dt:
05/05/2009
Application #:
12124119
Filing Dt:
05/20/2008
Title:
SYSTEM AND METHOD FOR AUTO-ROUTING JOG ELIMINATION
48
Patent #:
7530042
Issue Dt:
05/05/2009
Application #:
12124120
Filing Dt:
05/20/2008
Title:
SYSTEM AND METHOD FOR AUTO-ROUTING JOG ELIMINATION
49
Patent #:
7962871
Issue Dt:
06/14/2011
Application #:
12126037
Filing Dt:
05/23/2008
Publication #:
US20090293030
Pub Dt:
11/26/2009
Title:
CONCURRENTLY MODELING DELAYS BETWEEN POINTS IN STATIC TIMING ANALYSIS OPERATION
50
Patent #:
7934180
Issue Dt:
04/26/2011
Application #:
12127051
Filing Dt:
05/27/2008
Publication #:
US20090300559
Pub Dt:
12/03/2009
Title:
INCREMENTAL SPECULATIVE MERGING
51
Patent #:
7890903
Issue Dt:
02/15/2011
Application #:
12129127
Filing Dt:
05/29/2008
Publication #:
US20090300560
Pub Dt:
12/03/2009
Title:
METHOD AND SYSTEM FOR FORMAL VERIFICATION OF AN ELECTRONIC CIRCUIT DESIGN
52
Patent #:
7934134
Issue Dt:
04/26/2011
Application #:
12133830
Filing Dt:
06/05/2008
Publication #:
US20090307548
Pub Dt:
12/10/2009
Title:
METHOD AND APPARATUS FOR PERFORMING LOGIC BUILT-IN SELF-TESTING OF AN INTEGRATED CIRCUIT
53
Patent #:
8122407
Issue Dt:
02/21/2012
Application #:
12137616
Filing Dt:
06/12/2008
Publication #:
US20090310870
Pub Dt:
12/17/2009
Title:
METHOD AND SYSTEM FOR IMPLEMENTING PATTERN MATCHING OF INTEGRATED CIRCUIT FEATURES USING VORONOI DIAGRAMS
54
Patent #:
7949989
Issue Dt:
05/24/2011
Application #:
12147169
Filing Dt:
06/26/2008
Publication #:
US20090327988
Pub Dt:
12/31/2009
Title:
METHODS, SYSTEMS AND COMPUTER PROGRAM PRODUCTS FOR LAYOUT DEVICE MATCHING DRIVEN BY A SCHEMATIC EDITOR
55
Patent #:
7873890
Issue Dt:
01/18/2011
Application #:
12164699
Filing Dt:
06/30/2008
Publication #:
US20090327824
Pub Dt:
12/31/2009
Title:
TECHNIQUES FOR PERFORMING A LOGIC BUILT-IN SELF-TEST IN AN INTEGRATED CIRCUIT DEVICE
56
Patent #:
7519927
Issue Dt:
04/14/2009
Application #:
12166561
Filing Dt:
07/02/2008
Title:
WIRING METHODS TO REDUCE METAL VARIATION EFFECTS ON LAUNCH-CAPTURE CLOCK PAIRS IN ORDER TO MINIMIZE CYCLE-TIME OVERLAP VIOLATIONS
57
Patent #:
7503024
Issue Dt:
03/10/2009
Application #:
12169447
Filing Dt:
07/08/2008
Title:
METHOD FOR HIERARCHICAL VLSI MASK LAYOUT DATA INTERROGATION
58
Patent #:
8086972
Issue Dt:
12/27/2011
Application #:
12174650
Filing Dt:
07/17/2008
Publication #:
US20100017764
Pub Dt:
01/21/2010
Title:
FUNCTIONAL VERIFICATION OF POWER GATED DESIGNS BY COMPOSITIONAL REASONING
59
Patent #:
7797652
Issue Dt:
09/14/2010
Application #:
12174924
Filing Dt:
07/17/2008
Publication #:
US20100017762
Pub Dt:
01/21/2010
Title:
IMPLEMENTING INTEGRATED CIRCUIT YIELD ESTIMATION USING VORONOI DIAGRAMS
60
Patent #:
7962877
Issue Dt:
06/14/2011
Application #:
12185943
Filing Dt:
08/05/2008
Publication #:
US20100037198
Pub Dt:
02/11/2010
Title:
PORT ASSIGNMENT IN HIERARCHICAL DESIGNS BY ABSTRACTING MACRO LOGIC
61
Patent #:
8166426
Issue Dt:
04/24/2012
Application #:
12191732
Filing Dt:
08/14/2008
Publication #:
US20100042569
Pub Dt:
02/18/2010
Title:
APPROXIMATION OF A CLOCK GATING FUNCTION VIA BDD PATH ELIMINATION
62
Patent #:
8136062
Issue Dt:
03/13/2012
Application #:
12200016
Filing Dt:
08/28/2008
Publication #:
US20100058270
Pub Dt:
03/04/2010
Title:
HIERARCHY REASSEMBLER FOR 1XN VLSI DESIGN
63
Patent #:
8132134
Issue Dt:
03/06/2012
Application #:
12200076
Filing Dt:
08/28/2008
Publication #:
US20100058271
Pub Dt:
03/04/2010
Title:
CLOSED-LOOP 1XN VLSI DESIGN SYSTEM
64
Patent #:
8122399
Issue Dt:
02/21/2012
Application #:
12200121
Filing Dt:
08/28/2008
Publication #:
US20100058272
Pub Dt:
03/04/2010
Title:
COMPILER FOR CLOSED-LOOP 1XN VLSI DESIGN
65
Patent #:
8141016
Issue Dt:
03/20/2012
Application #:
12201591
Filing Dt:
08/29/2008
Publication #:
US20100058260
Pub Dt:
03/04/2010
Title:
INTEGRATED DESIGN FOR MANUFACTURING FOR 1XN VLSI DESIGN
66
Patent #:
7966598
Issue Dt:
06/21/2011
Application #:
12201643
Filing Dt:
08/29/2008
Publication #:
US20100058275
Pub Dt:
03/04/2010
Title:
TOP LEVEL HIERARCHY WIRING VIA 1XN COMPILER
67
Patent #:
7930610
Issue Dt:
04/19/2011
Application #:
12206781
Filing Dt:
09/09/2008
Publication #:
US20100064190
Pub Dt:
03/11/2010
Title:
SYSTEM AND METHOD FOR POWER REDUCTION THROUGH POWER AWARE LATCH WEIGHTING OF COMPLEX SUB-CIRCUITS
68
Patent #:
7895544
Issue Dt:
02/22/2011
Application #:
12207814
Filing Dt:
09/10/2008
Publication #:
US20100064264
Pub Dt:
03/11/2010
Title:
METHOD TO GRAPHICALLY IDENTIFY REGISTERS WITH UNBALANCED SLACK AS PART OF PLACEMENT DRIVEN SYNTHESIS OPTIMIZATION
69
Patent #:
8141017
Issue Dt:
03/20/2012
Application #:
12237482
Filing Dt:
09/25/2008
Publication #:
US20100077368
Pub Dt:
03/25/2010
Title:
METHOD FOR BOUNDED TRANSACTIONAL TIMING ANALYSIS
70
Patent #:
8104005
Issue Dt:
01/24/2012
Application #:
12244512
Filing Dt:
10/02/2008
Publication #:
US20100088658
Pub Dt:
04/08/2010
Title:
METHOD AND APPARATUS FOR EFFICIENT INCREMENTAL STATISTICAL TIMING ANALYSIS AND OPTIMIZATION
71
Patent #:
8086924
Issue Dt:
12/27/2011
Application #:
12250085
Filing Dt:
10/13/2008
Publication #:
US20100095177
Pub Dt:
04/15/2010
Title:
IMPLEMENTING DIAGNOSIS OF TRANSITIONAL SCAN CHAIN DEFECTS USING LOGIC BUILT IN SELF TEST (LBIST ) TEST PATTERNS.
72
Patent #:
8122401
Issue Dt:
02/21/2012
Application #:
12260837
Filing Dt:
10/29/2008
Title:
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR DETERMINING EQUIVALENCE OF NETLISTS UTILIZING AT LEAST ONE TRANSFORMATION
73
Patent #:
8117571
Issue Dt:
02/14/2012
Application #:
12260851
Filing Dt:
10/29/2008
Title:
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR DETERMINING EQUIVALENCE OF NETLISTS UTILIZING ABSTRACTIONS AND TRANSFORMATIONS
74
Patent #:
7921346
Issue Dt:
04/05/2011
Application #:
12262976
Filing Dt:
10/31/2008
Publication #:
US20100115337
Pub Dt:
05/06/2010
Title:
VERIFICATION OF ARRAY BUILT-IN SELF-TEST (ABIST) DESIGN-FOR-TEST/DESIGN-FOR-DIAGNOSTICS (DFT/DFD)
75
Patent #:
8103983
Issue Dt:
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Assignor
1
MENTOR GRAPHICS CORPORATION
Exec Dt:
12/30/2020
Newly Merged Entity Data
1
SIEMENS INDUSTRY SOFTWARE INC.
Exec Dt:
12/30/2020
Newly Merged Entity's New Name
1
SIEMENS INDUSTRY SOFTWARE INC.
5800 GRANITE PARKWAY, SUITE 600
PLANO, TEXAS 75024
Correspondence name and address
SIEMENS CORPORATION IP DEPT - MAIL CODE INT-244
3850 QUADRANGLE BOULEVARD
ORLANDO, FL 32817

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