Patent Assignment Details
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Reel/Frame: | 011097/0546 | |
| Pages: | 2 |
| | Recorded: | 09/18/2000 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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09427727
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Filing Dt:
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10/27/1999
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Title:
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0.7V TWO-PORT 6T SRAM MEMORY CELL STRUCTURE WITH SINGLE-BIT-LINE SIMULTANEOUS READ- AND WRITE ACCESS (SBLSRWA) CAPABILITY USING PARTIALLY-DEPLETED SOI CMOS DYNAMIC -THRESHOLD TECHNIQUE
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Assignee
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18FL, NO. 106, SEC.2 HO-PING E. RD. |
TAIPEI, TAIWAN R.O.C |
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Correspondence name and address
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THOMAS, KAYDEN, HORSTEMEYER & RISLEY LLP
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DANIEL R. MCCLURE
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100 GALLERIA PARKWAY, SUITE 1750
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ATLANTA, GA 30339
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