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Reel/Frame:057442/0549   Pages: 8
Recorded: 09/10/2021
Attorney Dkt #:MI22-7349
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
10/03/2023
Application #:
17026629
Filing Dt:
09/21/2020
Publication #:
Pub Dt:
03/24/2022
Title:
Integrated Circuitry, Method Used In The Fabrication Of A Vertical Transistor, And Method Used In The Fabrication Of Integrated Circuitry
Assignors
1
Exec Dt:
09/20/2020
2
Exec Dt:
09/09/2021
3
Exec Dt:
07/20/2020
Assignee
1
8000 SOUTH FEDERAL WAY, MS 1- 525
BOISE, IDAHO 83716
Correspondence name and address
WELLS ST. JOHN P.S.
601 W. MAIN AVENUE
SUITE 600
SPOKANE, WA 99201

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