Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 033666/0555 | |
| Pages: | 6 |
| | Recorded: | 09/04/2014 | | |
| Attorney Dkt #: | 303.737US* |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
7
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09940328
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Filing Dt:
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08/27/2001
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Publication #:
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Pub Dt:
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10/24/2002
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Title:
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ELECTRONIC DEVICE WITH INTERLEAVED PORTIONS FOR USE IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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10318971
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Filing Dt:
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12/13/2002
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Publication #:
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Pub Dt:
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05/15/2003
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Title:
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INTEGRATED CIRCUIT MEMORY WITH OFFSET CAPACITOR
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Patent #:
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Issue Dt:
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07/05/2005
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Application #:
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10318972
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Filing Dt:
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12/13/2002
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Publication #:
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Pub Dt:
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05/15/2003
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Title:
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METHOD FOR STABILIZING OR OFFSETTING VOLTAGE IN AN INTEGRATED CIRCUIT
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11126015
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Filing Dt:
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05/10/2005
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Publication #:
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Pub Dt:
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10/06/2005
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Title:
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Method for stabilizing or offsetting voltage in an integrated circuit
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Patent #:
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Issue Dt:
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01/05/2010
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Application #:
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11379441
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Filing Dt:
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04/20/2006
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Publication #:
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Pub Dt:
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09/07/2006
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Title:
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MULTI-RESISTIVE INTEGRATED CIRCUIT MEMORY
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Patent #:
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Issue Dt:
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01/10/2012
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Application #:
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12626110
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Filing Dt:
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11/25/2009
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Publication #:
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Pub Dt:
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03/25/2010
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Title:
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MULTI-RESISTIVE INTEGRATED CIRCUIT MEMORY
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Patent #:
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Issue Dt:
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11/04/2014
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Application #:
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13345417
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Filing Dt:
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01/06/2012
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Publication #:
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Pub Dt:
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04/26/2012
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Title:
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MULTI-RESISTIVE INTEGRATED CIRCUIT MEMORY
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Assignee
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| 8000 SO FEDERAL WAY |
| BOISE, IDAHO 83716 |
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Correspondence name and address
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SCHWEGMAN, LUNDBERG & WOESSNER, P.A.
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P. O. BOX 2938
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MINNEAPOLIS, MN 55402-0938
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