Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 007179/0557 | |
| Pages: | 5 |
| | Recorded: | 10/21/1994 | | |
| Conveyance: | CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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12/19/1995
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Application #:
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08179904
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Filing Dt:
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01/11/1994
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Title:
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BI-PLANAR MULTI-CHIP MODULE
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Patent #:
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Issue Dt:
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07/14/1998
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Application #:
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08179926
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Filing Dt:
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01/11/1994
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Title:
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DUAL-INSTRUCTION-SET ARCHITECTURE CPU WITH HIDDEN SOFTWARE EMULATION MODE
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Patent #:
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Issue Dt:
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08/15/1995
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Application #:
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08207751
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Filing Dt:
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03/08/1994
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Title:
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SIGN-EXTENSION OF IMMEDIATE CONSTANTS IN AN ALU
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Patent #:
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Issue Dt:
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08/08/1995
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Application #:
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08207857
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Filing Dt:
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03/08/1994
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Title:
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EMULATION OF SEGMENT BOUNDS CHECKING USING PAGING WITH SUB-PAGE VALIDITY
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Assignee
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| 2001 GATEWAY PLACE, SUITE 601 W |
| SAN JOSE, CALIFORNIA 95110 |
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Correspondence name and address
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STUART T. AUVINEN
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429 26TH AVE.
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SANTA CRUZ, CA 95062
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