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Patent Assignment Details
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Reel/Frame:061301/0567   Pages: 9
Recorded: 08/23/2022
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 060646 FRAME: 0916. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.
Total properties: 18
1
Patent #:
Issue Dt:
06/08/2004
Application #:
09706450
Filing Dt:
11/03/2000
Title:
PROGRAMMABLE SERIAL PORT ARCHITECTURE AND SYSTEM
2
Patent #:
Issue Dt:
02/10/2004
Application #:
10127909
Filing Dt:
04/22/2002
Title:
GAIN STAGE THAT MINIMIZES THE MILLER EFFECT
3
Patent #:
Issue Dt:
03/11/2008
Application #:
11039948
Filing Dt:
01/24/2005
Publication #:
Pub Dt:
10/27/2005
Title:
METHOD FOR PROCESSING NOISE INTERFERENCE
4
Patent #:
Issue Dt:
02/03/2009
Application #:
11625368
Filing Dt:
01/22/2007
Publication #:
Pub Dt:
07/24/2008
Title:
MEMORY SYSTEMS AND MEMORY ACCESS METHODS
5
Patent #:
Issue Dt:
08/30/2011
Application #:
11889152
Filing Dt:
08/09/2007
Publication #:
Pub Dt:
01/31/2008
Title:
METHOD FOR PROCESSING NOISE INTERFERENCE
6
Patent #:
Issue Dt:
12/27/2011
Application #:
11960555
Filing Dt:
12/19/2007
Publication #:
Pub Dt:
05/01/2008
Title:
METHOD FOR PROCESSING NOISE INTERFERENCE
7
Patent #:
Issue Dt:
03/02/2010
Application #:
11967264
Filing Dt:
12/31/2007
Publication #:
Pub Dt:
07/02/2009
Title:
SIGE DEVICE WITH SIGE-EMBEDDED DUMMY PATTERN FOR ALLEVIATING MICRO-LOADING EFFECT
8
Patent #:
Issue Dt:
03/26/2013
Application #:
12817387
Filing Dt:
06/17/2010
Publication #:
Pub Dt:
12/22/2011
Title:
COMPUTING SYSTEM PROVIDING NORMAL SECURITY AND HIGH SECURITY SERVICES
9
Patent #:
Issue Dt:
03/11/2014
Application #:
12940022
Filing Dt:
11/04/2010
Publication #:
Pub Dt:
05/10/2012
Title:
SEMICONDUCTOR STRUCTURE WITH MULTI-LAYER CONTACT ETCH STOP LAYER STRUCTURE
10
Patent #:
Issue Dt:
09/30/2014
Application #:
13617394
Filing Dt:
09/14/2012
Publication #:
Pub Dt:
04/11/2013
Title:
LOW POWER MEMORY CONTROLLERS
11
Patent #:
Issue Dt:
07/19/2016
Application #:
14020367
Filing Dt:
09/06/2013
Publication #:
Pub Dt:
03/13/2014
Title:
GUARD RING STRUCTURE AND METHOD FOR FORMING THE SAME
12
Patent #:
Issue Dt:
09/29/2015
Application #:
14051548
Filing Dt:
10/11/2013
Publication #:
Pub Dt:
04/16/2015
Title:
SEMICONDUCTOR PACKAGE
13
Patent #:
Issue Dt:
06/28/2016
Application #:
14636137
Filing Dt:
03/02/2015
Publication #:
Pub Dt:
06/30/2016
Title:
FLIP CHIP SCHEME AND METHOD OF FORMING FLIP CHIP SCHEME
14
Patent #:
Issue Dt:
07/12/2016
Application #:
14824210
Filing Dt:
08/12/2015
Publication #:
Pub Dt:
12/03/2015
Title:
SEMICONDUCTOR PACKAGE
15
Patent #:
Issue Dt:
10/31/2017
Application #:
15185063
Filing Dt:
06/17/2016
Publication #:
Pub Dt:
10/13/2016
Title:
SEMICONDUCTOR PACKAGE
16
Patent #:
Issue Dt:
04/17/2018
Application #:
15186937
Filing Dt:
06/20/2016
Publication #:
Pub Dt:
10/13/2016
Title:
GUARD RING STRUCTURE AND METHOD FOR FORMING THE SAME
17
Patent #:
Issue Dt:
12/25/2018
Application #:
15718141
Filing Dt:
09/28/2017
Publication #:
Pub Dt:
01/18/2018
Title:
SEMICONDUCTOR PACKAGE
18
Patent #:
Issue Dt:
01/01/2019
Application #:
15911414
Filing Dt:
03/05/2018
Publication #:
Pub Dt:
07/05/2018
Title:
GUARD RING STRUCTURE AND METHOD FOR FORMING THE SAME
Assignor
1
Exec Dt:
12/26/2021
Assignee
1
5204 BLUEWATER DR
FRISCO, TEXAS 75036
Correspondence name and address
DO KIM
8105 RASOR BLVD STE 210
PLANO, TX 75024

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