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Patent #:
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Issue Dt:
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03/06/2012
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Application #:
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12572221
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Filing Dt:
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10/01/2009
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Publication #:
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Pub Dt:
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01/28/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING AT LEAST SIX LINEAR-SHAPED CONDUCTIVE STRUCTURES FORMING GATE ELECTRODES OF TRANSISTORS WITH AT LEAST TWO DIFFERENT EXTENSION DISTANCES BEYOND CONDUCTIVE CONTACTING STRUCTURES
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Patent #:
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Issue Dt:
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05/07/2013
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Application #:
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12572225
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Filing Dt:
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10/01/2009
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Publication #:
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Pub Dt:
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01/28/2010
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Title:
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SEMICONDUCTOR DEVICE WITH GATE LEVEL INCLUDING GATE ELECTRODE CONDUCTORS FOR TRANSISTORS OF FIRST TYPE AND TRANSISTOR OF SECOND TYPE WITH SOME GATE ELECTRODE CONDUCTORS OF DIFFERENT LENGTH
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Patent #:
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Issue Dt:
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09/04/2012
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Application #:
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12572228
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Filing Dt:
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10/01/2009
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Publication #:
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Pub Dt:
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02/04/2010
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Title:
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SEMICONDUCTOR DEVICE WITH GATE LEVEL INCLUDING TRANSISTORS OF FIRST TYPE AND TRANSISTORS OF SECOND TYPE WITH CORRESPONDING GATE CONTACT PLACEMENT RESTRICTION
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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12572229
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Filing Dt:
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10/01/2009
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Publication #:
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Pub Dt:
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02/04/2010
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Title:
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SEMICONDUCTOR DEVICE WITH LINEARLY RESTRICTED GATE LEVEL REGION INCLUDING FOUR TRANSISTORS OF FIRST TYPE AND FOUR TRANSISTORS OF SECOND TYPE WITH GATE DEFINING SHAPES OF DIFFERENT LENGTH
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Patent #:
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Issue Dt:
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01/03/2012
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Application #:
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12572232
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Filing Dt:
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10/01/2009
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Publication #:
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Pub Dt:
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02/04/2010
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Title:
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METHOD FOR FABRICATING INTEGRATED CIRCUIT WITH GATE ELECTRODE LEVEL REGION INCLUDING TWO SIDE-BY-SIDE ONES OF AT LEAST THREE LINEAR-SHAPED CONDUCTIVE STRUCTURES ELECTRICALLY CONNECTED TO EACH OTHER THROUGH NON-GATE LEVEL
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Patent #:
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Issue Dt:
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03/13/2012
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Application #:
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12572237
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Filing Dt:
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10/01/2009
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Publication #:
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Pub Dt:
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02/04/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING AT LEAST THREE LINEAR-SHAPED CONDUCTIVE STRUCTURES AT EQUAL PITCH INCLUDING LINEAR-SHAPED CONDUCTIVE STRUCTURE HAVING NON-GATE PORTION LENGTH GREATER THAN GATE PORTION LENGTH
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Patent #:
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Issue Dt:
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03/06/2012
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Application #:
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12572239
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Filing Dt:
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10/01/2009
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Publication #:
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Pub Dt:
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02/04/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING AT LEAST SIX LINEAR-SHAPED CONDUCTIVE STRUCTIVE STRUCTURES AT EQUAL PITCH INCLUDING AT LEAST TWO LINEAR-SHAPED CONDUCTIVE STRUCTURES HAVING NON-GATE PORTIONS OF DIFFERENT LENGTH
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Patent #:
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Issue Dt:
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09/04/2012
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Application #:
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12572243
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Filing Dt:
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10/01/2009
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Publication #:
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Pub Dt:
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02/04/2010
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Title:
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SEMICONDUCTOR DEVICE INCLUDING AT LEAST SIX TRANSISTOR FORMING LINEAR SHAPES WITH AT LEAST TWO TRANSISTOR FORMING LINEAR SHAPES HAVING OFFSET ENDS
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Patent #:
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Issue Dt:
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05/22/2012
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Application #:
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12717885
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Filing Dt:
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03/04/2010
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Publication #:
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Pub Dt:
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07/01/2010
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Title:
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METHODS FOR GATE-LENGTH BIASING USING ANNOTATION DATA
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Patent #:
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Issue Dt:
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07/16/2013
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Application #:
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12717887
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Filing Dt:
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03/04/2010
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Publication #:
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Pub Dt:
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07/01/2010
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Title:
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STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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12753711
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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07/29/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING TWO COMPLEMENTARY PAIRS OF CO-ALIGNED GATE ELECTRODES WITH OFFSET CONTACTING STRUCTURES POSITIONED BETWEEN TRANSISTORS OF DIFFERENT TYPE
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Patent #:
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Issue Dt:
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03/26/2013
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Application #:
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12753727
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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10/07/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING GATE ELECTRODE LEVEL REGION INCLUDING CROSS-COUPLED TRANSISTORS HAVING AT LEAST ONE GATE CONTACT LOCATED OVER OUTER PORTION OF GATE ELECTRODE LEVEL REGION
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Patent #:
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Issue Dt:
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03/25/2014
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Application #:
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12753733
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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07/29/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN AT LEAST NINE GATE LEVEL FEATURE LAYOUT CHANNELS
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Patent #:
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Issue Dt:
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03/11/2014
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Application #:
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12753740
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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07/29/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN AT LEAST TWELVE GATE LEVEL FEATURE LAYOUT CHANNELS
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Patent #:
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Issue Dt:
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07/22/2014
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Application #:
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12753753
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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07/29/2010
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Title:
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Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Electrical Connection of Cross- Coupled Transistors Through Same Interconnect Layer
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Patent #:
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Issue Dt:
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03/12/2013
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Application #:
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12753758
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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10/07/2010
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Title:
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LINEAR GATE LEVEL CROSS-COUPLED TRANSISTOR DEVICE WITH NON-OVERLAPPING PMOS TRANSISTORS AND NON-OVERLAPPING NMOS TRANSISTORS RELATIVE TO DIRECTION OF GATE ELECTRODES
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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12753766
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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10/07/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS WITH TWO TRANSISTORS OF DIFFERENT TYPE HAVING GATE ELECTRODES FORMED BY COMMON GATE LEVEL FEATURE WITH SHARED DIFFUSION REGIONS ON OPPOSITE SIDES OF COMMON GATE LEVEL FEATURE
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Patent #:
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Issue Dt:
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07/22/2014
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Application #:
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12753776
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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07/29/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH TWO INSIDE POSITIONED GATE CONTACTS AND TWO OUTSIDE POSITIONED GATE CONTACTS AND ELECTRICAL CONNECTION OF CROSS-COUPLED TRANSISTORS THROUGH SAME INTERCONNECT LAYER
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Patent #:
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Issue Dt:
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11/12/2013
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Application #:
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12753789
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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07/29/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRASISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH FOUR INSIDE POSITIONED GATE CONTACTS HAVING OFFSET RELATIONSHIPS AND ELECTRICAL CONNECTION OF CROSS-COUPLED TRANSISTORS THROUGH SAME I
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Patent #:
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Issue Dt:
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07/08/2014
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Application #:
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12753793
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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07/29/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH FOUR INSIDE POSITIONED GATE CONTACTS HAVING OFFSET AND ALIGNED RELATIONSHIPS AND ELECTRICAL CONNECTION OF TRANSISTOR GATES THROUGH LI
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Patent #:
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Issue Dt:
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09/04/2012
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Application #:
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12753795
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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07/29/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS WITH TWO TRANSISTORS OF DIFFERENT TYPE FORMED BY SAME GATE LEVEL STRUCTURE AND TWO TRANSISTORS OF DIFFERENT TYPE FORMED BY SEPARATE GATE LEVEL STRUCTURES
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Patent #:
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Issue Dt:
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03/26/2013
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Application #:
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12753798
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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07/29/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH SHARED DIFFUSION REGIONS ON OPPOSITE SIDES OF TWO-TRANSISTOR-FORMING GATE LEVEL FEATURE
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Patent #:
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Issue Dt:
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11/19/2013
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Application #:
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12753805
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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07/29/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH FOUR INSIDE POSITIONED GATE CONTACTS AND ELECTRICAL CONNECTION OF TRANSISTOR GATES THROUGH LINEAR INTERCONNECT CONDUCTORS IN SINGLE I
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Patent #:
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Issue Dt:
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11/12/2013
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Application #:
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12753810
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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07/29/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH FOUR INSIDE POSITIONED GATE CONTACTS HAVING OFFSET AND ALIGNED RELATIONSHIPS
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Patent #:
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Issue Dt:
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11/15/2011
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Application #:
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12753817
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Filing Dt:
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04/02/2010
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Publication #:
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Pub Dt:
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09/23/2010
| | | | |
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Title:
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SEMICONDUCTOR DEVICE INCLUDING CROSS-COUPLED TRANSISTORS FORMED FROM LINEAR-SHAPED GATE LEVEL FEATURES
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Patent #:
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Issue Dt:
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05/20/2014
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Application #:
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12754050
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
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07/29/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS
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Patent #:
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Issue Dt:
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10/22/2013
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Application #:
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12754061
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
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09/23/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH AT LEAST TWO DIFFERENT GATE LEVEL FEATURE EXTENSIONS BEYOND CONTACT
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Patent #:
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Issue Dt:
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05/27/2014
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Application #:
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12754078
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
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07/29/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH SERIALLY CONNECTED TRANSISTORS
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Patent #:
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Issue Dt:
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11/05/2013
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Application #:
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12754091
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
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09/23/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH AT LEAST TWO DIFFERENT GATE LEVEL FEATURE INNER EXTENSIONS BEYOND GATE ELECTRODE
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Patent #:
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Issue Dt:
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06/03/2014
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Application #:
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12754103
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
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07/29/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH GATE CONTACT POSITION SPECIFICATIONS
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Patent #:
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Issue Dt:
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10/15/2013
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Application #:
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12754114
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
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09/23/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH AT LEAST TWO GATE ELECTRODES ELECTRICALLY CONNECTED TO EACH OTHER THROUGH GATE LEVEL FEATURE
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Patent #:
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Issue Dt:
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10/08/2013
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Application #:
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12754129
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
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09/23/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH SHARED DIFFUSION REGIONS ON OPPOSITE SIDES OF TWO-TRANSISTOR-FORMING GATE LEVEL FEATURE AND ELECTRICAL CONNECTION OF TRANSISTOR GATES
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Patent #:
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Issue Dt:
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10/29/2013
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Application #:
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12754147
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
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10/07/2010
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH AT LEAST ONE GATE LEVEL FEATURE EXTENDING INTO ADJACENT GATE LEVEL FEATURE LAYOUT CHANNEL
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Patent #:
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Issue Dt:
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08/26/2014
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Application #:
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12754168
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
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07/29/2010
| | | | |
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Title:
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Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Gate Level Feature Layout Channel Including Single Transistor
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Patent #:
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Issue Dt:
|
06/03/2014
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Application #:
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12754215
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
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07/29/2010
| | | | |
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Title:
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Integrated Circuit including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Outer Positioned Gate Contacts
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Patent #:
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Issue Dt:
|
10/21/2014
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Application #:
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12754233
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
|
07/29/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH AT LEAST TWO GATE ELECTRODES ELECTRICALLY CONNECTED TO EACH OTHER THROUGH ANOTHER TRANSISTOR FORMING GATE LEVEL FEATURE
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Patent #:
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Issue Dt:
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09/25/2012
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Application #:
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12754351
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
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07/29/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH GATE CONTACT POSITION AND OFFSET SPECIFICATIONS
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Patent #:
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Issue Dt:
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10/08/2013
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Application #:
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12754384
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
|
10/07/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH OTHER TRANSISTORS POSITIONED BETWEEN CROSS-COUPLED TRANSISTORS
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Patent #:
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Issue Dt:
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03/11/2014
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Application #:
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12754563
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
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07/29/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH GATE CONTACT POSITION, ALIGNMENT, AND OFFSET SPECIFICATIONS
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Patent #:
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Issue Dt:
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09/16/2014
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Application #:
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12754566
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
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10/14/2010
| | | | |
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH GATE ELECTRODE PLACEMENT SPECIFICATIONS
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Patent #:
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Issue Dt:
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02/07/2017
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Application #:
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12775429
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Filing Dt:
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05/06/2010
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Publication #:
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Pub Dt:
|
11/11/2010
| | | | |
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Title:
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CELL CIRCUIT AND LAYOUT WITH LINEAR FINFET STRUCTURES
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Patent #:
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Issue Dt:
|
08/09/2011
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Application #:
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12814411
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Filing Dt:
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06/11/2010
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Publication #:
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Pub Dt:
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10/07/2010
| | | | |
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Title:
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METHODS, STRUCTURES, AND DESIGNS FOR SELF-ALIGNING LOCAL INTERCONNECTS USED IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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02/25/2014
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Application #:
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12904134
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Filing Dt:
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10/13/2010
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Publication #:
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04/14/2011
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METHODS FOR CELL BOUNDARY ENCROACHMENT AND LAYOUTS IMPLEMENTING THE SAME
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NONE
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12981151
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12/29/2010
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06/30/2011
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Title:
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Methods for Consumption of Timing Margin to Reduce Power Utilization in Integrated Circuitry and Device Implementing the Same
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06/24/2014
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13007582
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01/14/2011
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05/12/2011
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SEMICONDUCTOR DEVICE WITH DYNAMIC ARRAY SECTIONS DEFINED AND PLACED ACCORDING TO MANUFACTURING ASSURANCE HALOS
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10/09/2012
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13007584
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01/14/2011
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Pub Dt:
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05/12/2011
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Title:
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SEMICONDUCTOR DEVICE WITH DYNAMIC ARRAY SECTIONS DEFINED AND PLACED ACCORDING TO MANUFACTURING ASSURANCE HALOS
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06/17/2014
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13047474
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03/14/2011
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06/30/2011
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Title:
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METHODS FOR DESIGNING SEMICONDUCTOR DEVICE WITH DYNAMIC ARRAY SECTION
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01/15/2013
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13073994
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03/28/2011
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07/21/2011
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Title:
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INTEGRATED CIRCUIT DEVICE INCLUDING DYNAMIC ARRAY SECTION WITH GATE LEVEL HAVING LINEAR CONDUCTIVE FEATURES ON AT LEAST THREE SIDE-BY-SIDE LINES AND UNIFORM LINE END SPACINGS
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06/25/2013
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13085447
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04/12/2011
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08/18/2011
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METHODS FOR MULTI-WIRE ROUTING AND APPARATUS IMPLEMENTING SAME
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03/25/2014
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13189433
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07/22/2011
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11/17/2011
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Methods, Structures, and Designs for Self-Aligning Local Interconnects used in Integrated Circuits
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09/16/2014
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13312673
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12/06/2011
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06/07/2012
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SCALABLE META-DATA OBJECTS
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10/13/2015
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13373470
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11/14/2011
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05/17/2012
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Methods for linewidth modification and apparatus implementing the same
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07/01/2014
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13464484
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05/04/2012
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08/29/2013
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SYSTEM AND METHOD OF LOADING A TRANSACTION CARD AND PROCESSING REPAYMENT ON A MOBILE DEVICE
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02/25/2014
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13473439
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05/16/2012
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05/23/2013
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COARSE GRID DESIGN METHODS AND STRUCTURES
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10/01/2013
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13540529
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07/02/2012
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11/01/2012
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METHODS FOR CELL PHASING AND PLACEMENT IN DYNAMIC ARRAY ARCHITECTURE AND IMPLEMENTATION OF THE SAME
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11/26/2013
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13589028
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08/17/2012
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12/06/2012
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Title:
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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS WITH TWO TRANSISTORS OF DIFFERENT TYPE HAVING GATE ELECTRODES FORMED BY COMMON GATE LEVEL FEATURE WITH SHARED DIFFUSION REGIONS ON OPPOSITE SIDES OF COMMON GATE LEVEL FEATURE
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08/25/2015
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13591141
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08/21/2012
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08/22/2013
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Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Gate Contact Position and Offset Specifications
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02/03/2015
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13620669
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09/14/2012
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09/26/2013
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Standard Cells having transistors annotated for gate-length biasing
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01/21/2014
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13620681
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09/14/2012
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01/10/2013
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STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING
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10/21/2014
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13620683
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09/14/2012
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01/10/2013
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STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING
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06/17/2014
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13620690
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09/14/2012
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Pub Dt:
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01/10/2013
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Title:
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STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING
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09/19/2017
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13686982
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11/28/2012
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08/29/2013
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SYSTEM AND METHOD FOR PROCESSING PAYMENT DURING AN ELECTRONIC COMMERCE TRANSACTION
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04/14/2015
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13740191
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01/12/2013
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05/23/2013
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CIRCUITS WITH LINEAR FINFET STRUCTURES
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10/07/2014
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13741298
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01/14/2013
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05/16/2013
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Title:
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Integrated Circuit Including Gate Electrode Level Region Including Cross-Coupled Transistors Having Gate Contacts Located Over Inner Portion of Gate Electrode Level Region and Offset Gate Level Feature Line Ends
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10/28/2014
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13741305
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01/14/2013
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06/13/2013
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Title:
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Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Shared Diffusion Regions on Opposite Sides of Two-Transistor-Forming Gate Level Feature
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NONE
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13774919
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02/22/2013
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06/27/2013
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INTEGRATED CIRCUIT INCLUDING GATE ELECTRODE TRACKS INCLUDING OFFSET END-TO-END SPACINGS
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NONE
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13774940
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02/22/2013
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07/04/2013
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Title:
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SEMICONDUCTOR CHIP INCLUDING GATE ELECTRODE FEATURES FORMED FROM GATE ELECTRODE FEATURE LAYOUT SHAPES ON GATE HORIZONTAL GRID AND INCLUDING FIRST-METAL FEATURES FORMED FROM FIRST-METAL FEATURE LAYOUT SHAPES ON FIRST-METAL VERITCAL GRID
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NONE
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13774954
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02/22/2013
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07/04/2013
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Integrated Circuit Including Gate Electrode Tracks That Each Form Gate Electrodes of Different Transistor Types With Intervening Non-Gate-Forming Gate Electrode Track
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02/10/2015
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13774970
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02/22/2013
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Pub Dt:
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07/11/2013
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Integrated Circuit Including At Least Four Linear-Shaped Conductive Structures Having Extending Portions of Different Length
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09/02/2014
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13827615
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03/14/2013
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08/08/2013
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INTEGRATED CIRCUIT WITH OFFSET LINE END SPACINGS IN LINEAR GATE ELECTRODE LEVEL
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12/30/2014
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13827755
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03/14/2013
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09/26/2013
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INTEGRATED CIRCUIT INCLUDING LINEAR GATE ELECTRODE STRUCTURES HAVING DIFFERENT EXTENSION DISTANCES BEYOND CONTACT
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07/10/2018
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13831530
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03/14/2013
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08/08/2013
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CROSS-COUPLED TRANSISTOR CIRCUIT DEFINED ON TWO GATE ELECTRODE TRACKS
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05/12/2020
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13831605
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03/15/2013
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08/08/2013
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CROSS-COUPLED TRANSISTOR CIRCUIT DEFINED ON THREE GATE ELECTRODE TRACKS
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05/19/2020
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13831636
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03/15/2013
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08/15/2013
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CROSS-COUPLED TRANSISTOR CIRCUIT DEFINED ON FOUR GATE ELECTRODE TRACKS
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05/20/2014
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13831664
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03/15/2013
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08/15/2013
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Cross-Coupled Transistor Circuit Including Offset Inner Gate Contacts
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09/16/2014
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13831717
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03/15/2013
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08/15/2013
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Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track
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07/14/2015
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13831742
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03/15/2013
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08/01/2013
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Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track and Gate Node Connection Through Single Interconnect Layer
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05/27/2014
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13831811
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03/15/2013
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08/08/2013
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Title:
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CROSS-COUPLED TRANSISTOR CIRCUIT DEFINED ON THREE GATE ELECTRODE TRACKS WITH DIFFUSION REGIONS OF COMMON NODE ON OPPOSING SIDES OF SAME GATE ELECTRODE TRACK
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09/30/2014
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13831832
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03/15/2013
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08/08/2013
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CROSS-COUPLED TRANSISTOR CIRCUIT DEFINED HAVING DIFFUSION REGIONS OF COMMON NODE ON OPPOSING SIDES OF SAME GATE ELECTRODE TRACK WITH AT LEAST TWO NON-INNER POSITIONED GATE CONTACTS
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12/30/2014
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03/15/2013
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08/08/2013
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INTEGRATED CIRCUIT WITH GATE ELECTRODE CONDUCTIVE STRUCTURES HAVING OFFSET ENDS
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02/03/2015
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13837123
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03/15/2013
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08/15/2013
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Integrated Circuit Including Gate Electrode Conductive Structures With Different Extension Distances Beyond Contact
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10/14/2014
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03/15/2013
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08/15/2013
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Finfet Transistor Circuit
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04/15/2014
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05/17/2013
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09/26/2013
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ENFORCEMENT OF SEMICONDUCTOR STRUCTURE REGULARITY FOR LOCALIZED TRANSISTORS AND INTERCONNECT
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09/05/2017
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05/20/2013
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10/03/2013
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SEMICONDUCTOR CHIP INCLUDING A CHIP LEVEL BASED ON A LAYOUT THAT INCLUDES BOTH REGULAR AND IRREGULAR WIRES
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06/24/2014
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06/14/2013
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10/24/2013
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Methods for Multi-Wire Routing and Apparatus Implementing Same
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02/10/2015
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09/23/2013
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01/30/2014
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SUPER-SELF-ALIGNED CONTACTS AND METHOD FOR MAKING THE SAME
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02/24/2015
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09/27/2013
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02/06/2014
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METHODS FOR CELL PHASING AND PLACEMENT IN DYNAMIC ARRAY ARCHITECTURE AND IMPLEMENTATION OF THE SAME
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06/06/2017
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CIRCUITRY AND LAYOUTS FOR XOR AND XNOR LOGIC
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05/10/2016
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02/21/2014
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06/19/2014
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COARSE GRID DESIGN METHODS AND STRUCTURES
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02/23/2016
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02/21/2014
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06/19/2014
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01/19/2016
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02/24/2014
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06/19/2014
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04/25/2017
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06/26/2014
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Integrated Circuit Cell Library for Multiple Patterning
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12/01/2015
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03/17/2014
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07/17/2014
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10/07/2014
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Title:
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Integrated Circuit Within Semiconductor Chip Including Cross-Coupled Transistor Configuration
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Patent #:
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Issue Dt:
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12/01/2015
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Application #:
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14245852
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Filing Dt:
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04/04/2014
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Publication #:
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Pub Dt:
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08/07/2014
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Title:
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GATE-LENGTH BIASING FOR DIGITAL CIRCUIT OPTIMIZATION
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Patent #:
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Issue Dt:
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06/30/2015
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Application #:
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14270225
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Filing Dt:
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05/05/2014
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Publication #:
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Pub Dt:
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08/28/2014
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Title:
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STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING
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Patent #:
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Issue Dt:
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09/30/2014
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Application #:
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14273483
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Filing Dt:
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05/08/2014
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Publication #:
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Pub Dt:
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08/28/2014
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Title:
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SEMICONDUCTOR CHIP INCLUDING REGION HAVING CROSS-COUPLED TRANSISTOR CONFIGURATION WITH OFFSET ELECTRICAL CONNECTION AREAS ON GATE ELECTRODE FORMING CONDUCTIVE STRUCTURES AND AT LEAST TWO DIFFERENT INNER EXTENSION DISTANCES OF GATE ELECTRODE FORMING CONDUCTIVE STRUC
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Patent #:
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Issue Dt:
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03/14/2017
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Application #:
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14276528
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Filing Dt:
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05/13/2014
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Publication #:
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Pub Dt:
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09/04/2014
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Title:
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SEMICONDUCTOR CHIP INCLUDING INTEGRATED CIRCUIT DEFINED WITHIN DYNAMIC ARRAY SECTION
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Patent #:
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Issue Dt:
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05/24/2016
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Application #:
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14284826
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Filing Dt:
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05/22/2014
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Publication #:
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Pub Dt:
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09/11/2014
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Title:
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SYSTEM AND METHOD OF LOADING A TRANSACTION CARD AND PROCESSING REPAYMENT ON A MOBILE DEVICE
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Patent #:
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Issue Dt:
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07/12/2016
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Application #:
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14298206
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Filing Dt:
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06/06/2014
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Publication #:
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Pub Dt:
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09/25/2014
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Title:
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Methods for Multi-Wire Routing and Apparatus Implementing Same
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