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Reel/Frame:044958/0571   Pages: 20
Recorded: 12/20/2017
Attorney Dkt #:22524-01000
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 40
1
Patent #:
Issue Dt:
07/22/2008
Application #:
10553873
Filing Dt:
10/21/2005
Publication #:
Pub Dt:
11/02/2006
Title:
SPLIT-CHANNEL ANTIFUSE ARRAY ARCHITECTURE
2
Patent #:
NONE
Issue Dt:
07/22/2008
Application #:
10553873
Filing Dt:
10/21/2005
Publication #:
Pub Dt:
11/02/2006
PCT #:
CA2005000701
Title:
SPLIT-CHANNEL ANTIFUSE ARRAY ARCHITECTURE
3
Patent #:
Issue Dt:
03/31/2009
Application #:
11618330
Filing Dt:
12/29/2006
Publication #:
Pub Dt:
07/19/2007
Title:
HIGH SPEED OTP SENSING SCHEME
4
Patent #:
Issue Dt:
07/13/2010
Application #:
11762552
Filing Dt:
06/13/2007
Publication #:
Pub Dt:
11/08/2007
Title:
ANTI-FUSE MEMORY CELL
5
Patent #:
Issue Dt:
01/05/2010
Application #:
11877229
Filing Dt:
10/23/2007
Publication #:
Pub Dt:
02/14/2008
Title:
SPLIT-CHANNEL ANTIFUSE ARRAY ARCHITECTURE
6
Patent #:
Issue Dt:
10/09/2012
Application #:
12139992
Filing Dt:
06/16/2008
Publication #:
Pub Dt:
10/09/2008
Title:
SPLIT-CHANNEL ANTIFUSE ARRAY ARCHITECTURE
7
Patent #:
Issue Dt:
01/13/2015
Application #:
12266828
Filing Dt:
11/07/2008
Publication #:
Pub Dt:
10/08/2009
Title:
LOW VT ANTIFUSE DEVICE
8
Patent #:
Issue Dt:
05/17/2011
Application #:
12306114
Filing Dt:
12/22/2008
Publication #:
Pub Dt:
10/22/2009
Title:
MASK PROGRAMMABLE ANTI-FUSE ARCHITECTURE
9
Patent #:
NONE
Issue Dt:
05/17/2011
Application #:
12306114
Filing Dt:
12/22/2008
Publication #:
Pub Dt:
10/22/2009
PCT #:
CA2007002287
Title:
MASK PROGRAMMABLE ANTI-FUSE ARCHITECTURE
10
Patent #:
Issue Dt:
10/19/2010
Application #:
12306260
Filing Dt:
12/23/2008
Publication #:
Pub Dt:
07/16/2009
Title:
PROGRAM LOCK CIRCUIT FOR A MASK PROGRAMMABLE ANTI-FUSE MEMORY ARRAY
11
Patent #:
NONE
Issue Dt:
10/19/2010
Application #:
12306260
Filing Dt:
12/23/2008
Publication #:
Pub Dt:
07/16/2009
PCT #:
CA2007002286
Title:
PROGRAM LOCK CIRCUIT FOR A MASK PROGRAMMABLE ANTI-FUSE MEMORY ARRAY
12
Patent #:
Issue Dt:
09/20/2011
Application #:
12306808
Filing Dt:
12/29/2008
Publication #:
Pub Dt:
11/26/2009
Title:
DUAL FUNCTION DATA REGISTER
13
Patent #:
NONE
Issue Dt:
09/20/2011
Application #:
12306808
Filing Dt:
12/29/2008
Publication #:
Pub Dt:
11/26/2009
PCT #:
CA2007002285
Title:
DUAL FUNCTION DATA REGISTER
14
Patent #:
Issue Dt:
05/10/2011
Application #:
12306940
Filing Dt:
12/30/2008
Publication #:
Pub Dt:
01/07/2010
Title:
POWER UP DETECTION SYSTEM FOR A MEMORY DEVICE
15
Patent #:
NONE
Issue Dt:
05/10/2011
Application #:
12306940
Filing Dt:
12/30/2008
Publication #:
Pub Dt:
01/07/2010
PCT #:
CA2007002316
Title:
POWER UP DETECTION SYSTEM FOR A MEMORY DEVICE
16
Patent #:
Issue Dt:
11/15/2011
Application #:
12342367
Filing Dt:
12/23/2008
Publication #:
Pub Dt:
10/08/2009
Title:
TEST CIRCUIT FOR AN UNPROGRAMMED OTP MEMORY ARRAY
17
Patent #:
Issue Dt:
07/27/2010
Application #:
12389933
Filing Dt:
02/20/2009
Publication #:
Pub Dt:
06/18/2009
Title:
HIGH SPEED OTP SENSING SCHEME
18
Patent #:
Issue Dt:
12/20/2011
Application #:
12442274
Filing Dt:
03/20/2009
Publication #:
Pub Dt:
01/14/2010
Title:
PROGRAM VERIFY METHOD FOR OTP MEMORIES
19
Patent #:
NONE
Issue Dt:
12/20/2011
Application #:
12442274
Filing Dt:
03/20/2009
Publication #:
Pub Dt:
01/14/2010
PCT #:
CA2007002284
Title:
PROGRAM VERIFY METHOD FOR OTP MEMORIES
20
Patent #:
Issue Dt:
06/25/2013
Application #:
12609605
Filing Dt:
10/30/2009
Publication #:
Pub Dt:
05/05/2011
Title:
AND-TYPE ONE TIME PROGRAMMABLE MEMORY CELL
21
Patent #:
Issue Dt:
07/03/2012
Application #:
12701140
Filing Dt:
02/05/2010
Publication #:
Pub Dt:
08/12/2010
Title:
HIGH RELIABILITY OTP MEMORY
22
Patent #:
Issue Dt:
07/17/2012
Application #:
12713991
Filing Dt:
02/26/2010
Publication #:
Pub Dt:
09/02/2010
Title:
LOW POWER ANTIFUSE SENSING SCHEME WITH IMPROVED RELIABILITY
23
Patent #:
Issue Dt:
09/27/2011
Application #:
12814124
Filing Dt:
06/11/2010
Publication #:
Pub Dt:
09/30/2010
Title:
ANTI-FUSE MEMORY CELL
24
Patent #:
Issue Dt:
03/06/2012
Application #:
12822332
Filing Dt:
06/24/2010
Publication #:
Pub Dt:
10/14/2010
Title:
HIGH SPEED OTP SENSING SCHEME
25
Patent #:
Issue Dt:
02/05/2013
Application #:
12843498
Filing Dt:
07/26/2010
Publication #:
Pub Dt:
01/27/2011
Title:
REDUNDANCY SYSTEM FOR NON-VOLATILE MEMORY
26
Patent #:
Issue Dt:
11/20/2012
Application #:
13219215
Filing Dt:
08/26/2011
Publication #:
Pub Dt:
12/22/2011
Title:
ANTI-FUSE MEMORY CELL
27
Patent #:
Issue Dt:
09/11/2012
Application #:
13229189
Filing Dt:
09/09/2011
Publication #:
Pub Dt:
12/29/2011
Title:
A METHOD FOR OPERATING A REGISTER STAGE OF A DUAL FUNCTION DATA REGISTER
28
Patent #:
Issue Dt:
09/03/2013
Application #:
13291520
Filing Dt:
11/08/2011
Publication #:
Pub Dt:
04/05/2012
Title:
TEST CELLS FOR AN UNPROGRAMMED OTP MEMORY ARRAY
29
Patent #:
Issue Dt:
07/01/2014
Application #:
13412500
Filing Dt:
03/05/2012
Publication #:
Pub Dt:
07/19/2012
Title:
METHODS FOR TESTING UNPROGRAMMED OTP MEMORY
30
Patent #:
Issue Dt:
09/08/2015
Application #:
13504295
Filing Dt:
04/26/2012
Publication #:
Pub Dt:
08/23/2012
Title:
OTP MEMORY CELL HAVING LOW CURRENT LEAKAGE
31
Patent #:
NONE
Issue Dt:
09/08/2015
Application #:
13504295
Filing Dt:
04/26/2012
Publication #:
Pub Dt:
08/23/2012
PCT #:
CA2010001700
Title:
OTP MEMORY CELL HAVING LOW CURRENT LEAKAGE
32
Patent #:
Issue Dt:
05/27/2014
Application #:
13662842
Filing Dt:
10/29/2012
Publication #:
Pub Dt:
03/07/2013
Title:
REVERSE OPTICAL PROXIMITY CORRECTION METHOD
33
Patent #:
Issue Dt:
02/18/2014
Application #:
13740747
Filing Dt:
01/14/2013
Publication #:
Pub Dt:
05/23/2013
Title:
REDUNDANCY SYSTEM FOR NON-VOLATILE MEMORY
34
Patent #:
Issue Dt:
05/12/2015
Application #:
13894824
Filing Dt:
05/15/2013
Publication #:
Pub Dt:
11/21/2013
Title:
POWER UP DETECTION SYSTEM FOR A MEMORY DEVICE
35
Patent #:
Issue Dt:
03/01/2016
Application #:
13896712
Filing Dt:
05/17/2013
Publication #:
Pub Dt:
11/21/2013
Title:
CIRCUIT AND METHOD FOR REDUCING WRITE DISTURB IN A NON-VOLATILE MEMORY DEVICE
36
Patent #:
Issue Dt:
09/01/2015
Application #:
14162380
Filing Dt:
01/23/2014
Publication #:
Pub Dt:
05/29/2014
Title:
REDUNDANCY SYSTEM FOR NON-VOLATILE MEMORY
37
Patent #:
Issue Dt:
09/01/2015
Application #:
14244499
Filing Dt:
04/03/2014
Publication #:
Pub Dt:
07/31/2014
Title:
ANTI-FUSE MEMORY CELL
38
Patent #:
Issue Dt:
09/06/2016
Application #:
15055972
Filing Dt:
02/29/2016
Publication #:
Pub Dt:
06/23/2016
Title:
CIRCUIT AND METHOD FOR REDUCING WRITE DISTURB IN A NON-VOLATILE MEMORY DEVICE
39
Patent #:
Issue Dt:
01/16/2018
Application #:
15247050
Filing Dt:
08/25/2016
Publication #:
Pub Dt:
11/23/2017
Title:
METHOD AND SYSTEM FOR POWER SIGNATURE SUPPRESSION IN MEMORY DEVICES
40
Patent #:
Issue Dt:
07/24/2018
Application #:
15395149
Filing Dt:
12/30/2016
Publication #:
Pub Dt:
07/13/2017
Title:
PUF VALUE GENERATION USING AN ANTI-FUSE MEMORY ARRAY
Assignor
1
Exec Dt:
12/12/2017
Assignee
1
690 EAST MIDDLEFIELD ROAD
MOUNTAIN VIEW, CALIFORNIA 94043
Correspondence name and address
DOHYUN AHN
FENWICK & WEST LLP
801 CALIFORNIA STREET
MOUNTAIN VIEW, CA 94041

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