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Patent Assignment Details
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Reel/Frame:010763/0572   Pages: 14
Recorded: 05/02/2000
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 157
Page 1 of 2
Pages: 1 2
1
Patent #:
5740380
Issue Dt:
04/14/1998
Application #:
08680464
Filing Dt:
07/15/1996
Title:
METHOD AND SYSTEM FOR APPORTIONING COMPUTER BUS BANDWIDTH
2
Patent #:
5905858
Issue Dt:
05/18/1999
Application #:
08742773
Filing Dt:
11/01/1996
Title:
SYSTEM AND METHOD FOR MEMORY ERROR HANDLING
3
Patent #:
6076182
Issue Dt:
06/13/2000
Application #:
08767180
Filing Dt:
12/16/1996
Title:
MEMORY FAULT CORRECTION SYSTEM AND METHOD
4
Patent #:
6141715
Issue Dt:
10/31/2000
Application #:
08826548
Filing Dt:
04/03/1997
Title:
METHOD AND SYSTEM FOR AVOIDING LIVELOCK CONDITIONS ON A COMPUTER BUS BY INSURING THAT THE FIRST RETIRED BUS MASTER IS THE FIRST TO RESUBMIT ITS RETIRED TRANSACTION
5
Patent #:
6044474
Issue Dt:
03/28/2000
Application #:
08826827
Filing Dt:
04/08/1997
Title:
MEMORY CONTROLLER WITH BUFFERED CAS/RAS EXTERNAL SYNCHRONIZATION CAPABILITY FOR REDUCING THE EFFECTS OF CLOCK-TO-SIGNAL SKEW
6
Patent #:
6047349
Issue Dt:
04/04/2000
Application #:
08873994
Filing Dt:
06/11/1997
Title:
SYSTEM FOR COMMUNICATING THROUGH A COMPUTER SYSTEM BUS BRIDGE
7
Patent #:
6076180
Issue Dt:
06/13/2000
Application #:
08880351
Filing Dt:
06/23/1997
Title:
METHOD FOR TESTING A CONTROLLER WITH RANDOM CONSTRAINTS
8
Patent #:
6249853
Issue Dt:
06/19/2001
Application #:
08882054
Filing Dt:
06/25/1997
Title:
GART AND PTES DEFINED BY CONFIGURATION REGISTERS
9
Patent #:
6282625
Issue Dt:
08/28/2001
Application #:
08882327
Filing Dt:
06/25/1997
Title:
GART AND PITES DEFINED BY CONFIGURAT ION REGISTERS
10
Patent #:
6069638
Issue Dt:
05/30/2000
Application #:
08882428
Filing Dt:
06/25/1997
Title:
SYSTEM FOR ACCELERATED GRAPHICS PORT ADDRESS REMAPPING INTERFACE TO MAIN MEMORY
11
Patent #:
6195734
Issue Dt:
02/27/2001
Application #:
08886525
Filing Dt:
07/02/1997
Title:
SYSTEM FOR IMPLEMENTING A GRAPHIC ADDRESS REMAPPING TABLE AS A VIRTUAL REGISTER FILE IN SYSTEM MEMORY
12
Patent #:
6202133
Issue Dt:
03/13/2001
Application #:
08887041
Filing Dt:
07/02/1997
Title:
METHOD OF PROCESSING MEMORY TRANSACTIONS IN A COMPUTER SYSTEM HAVING DUAL SYSTEM MEMORIES AND MEMORY CONTROLLERS
13
Patent #:
6049855
Issue Dt:
04/11/2000
Application #:
08887042
Filing Dt:
07/02/1997
Title:
A SEGMENTED MEMORY SYSTEM EMPLOYING DIFFERENT INTERLEAVING SCHEME FOR EACH DIFFERENT MEMEORY SEGMENT
14
Patent #:
6192457
Issue Dt:
02/20/2001
Application #:
08887868
Filing Dt:
07/02/1997
Title:
METHOD FOR IMPLEMENTING A GRAPHIC ADDRESS REMAPPING TABLE AS A VIRTUAL REGISTER FILE IN SYSTEM MEMORY
15
Patent #:
6378047
Issue Dt:
04/23/2002
Application #:
08888501
Filing Dt:
07/07/1997
Title:
SYSTEM AND METHOD FOR INVALIDATING CACHE MEMORY
16
Patent #:
6243769
Issue Dt:
06/05/2001
Application #:
08896936
Filing Dt:
07/18/1997
Title:
DYNAMIC BUFFER ALLOCATION FOR A COMPUTER SYSTEM
17
Patent #:
6073190
Issue Dt:
06/06/2000
Application #:
08896938
Filing Dt:
07/18/1997
Title:
SYSTEM FOR DYNAMIC BUFFER ALLOCATION COMPRISING CONTROL LOGIC FOR CONTROLLING A FIRST ADDRESS BUFFER AND A FIRST DATA BUFFER AS A MATCHED PAIR
18
Patent #:
6078977
Issue Dt:
06/20/2000
Application #:
08922243
Filing Dt:
09/02/1997
Title:
HIERARCHICAL BUS STRUTURE ACCESS SYSTEM
19
Patent #:
6047381
Issue Dt:
04/04/2000
Application #:
08925885
Filing Dt:
09/08/1997
Title:
VARIABLE SPEED CONTROLLER
20
Patent #:
6026463
Issue Dt:
02/15/2000
Application #:
08927233
Filing Dt:
09/10/1997
Title:
METHOD FOR IMPROVING DATA TRANSFER RATES FOR USER DATA STORED ON A DISK STORAGE DEVICE
21
Patent #:
6098068
Issue Dt:
08/01/2000
Application #:
08951993
Filing Dt:
10/16/1997
Title:
INTER-MODULE DATA MANAGEMENT METHODOLOGY FOR CIRCUIT SYNTHESIS
22
Patent #:
6055597
Issue Dt:
04/25/2000
Application #:
08960777
Filing Dt:
10/30/1997
Title:
BI-DIRECTIONAL SYNCHRONIZING BUFFER SYSTEM
23
Patent #:
6185664
Issue Dt:
02/06/2001
Application #:
08971834
Filing Dt:
11/17/1997
Title:
METHOD FOR PROVIDING ADDITIONAL LATENCY FOR SYNCHRONOUSLY ACCESSED MEMORY
24
Patent #:
5887414
Issue Dt:
03/30/1999
Application #:
08971973
Filing Dt:
11/17/1997
Title:
SOLID PACK FISH CANNING MACHINE
25
Patent #:
6092219
Issue Dt:
07/18/2000
Application #:
08984115
Filing Dt:
12/03/1997
Title:
METHOD FOR USE OF BUS PARKING STATES TO COMMUNICATE DIAGNOSTIC INFORMATION
26
Patent #:
6112316
Issue Dt:
08/29/2000
Application #:
08984393
Filing Dt:
12/03/1997
Title:
SYSTEM FOR USE OF BUS PARKING STATES TO COMMUNICATE DIAGNOSTIC INFORMATION
27
Patent #:
6040714
Issue Dt:
03/21/2000
Application #:
08990057
Filing Dt:
12/12/1997
Title:
METHOD FOR PROVIDING TWO MODES OF I/O PAD TERMINATION
28
Patent #:
6252612
Issue Dt:
06/26/2001
Application #:
09000511
Filing Dt:
12/30/1997
Title:
ACCELERATED GRAPHICS PORT FOR MULTIPLE MEMORY CONTROLLER COMPUTER SYSTEM
29
Patent #:
6157398
Issue Dt:
12/05/2000
Application #:
09000517
Filing Dt:
12/30/1997
Title:
METHOD OF IMPLEMENTING AN ACCELARATED GRAPHICS PORT FOR A MULTIPLE MEMORY CONTROLLER COMPUTER SYSTEM
30
Patent #:
6301645
Issue Dt:
10/09/2001
Application #:
09008899
Filing Dt:
01/20/1998
Title:
SYSTEM FOR ISSUING DEVICE REQUESTS BY PROXY
31
Patent #:
6108733
Issue Dt:
08/22/2000
Application #:
09008966
Filing Dt:
01/20/1998
Title:
METHOD FOR EXTENDING THE AVAILABLE NUMBER OF CONFIGURATION REGISTERS
32
Patent #:
6243775
Issue Dt:
06/05/2001
Application #:
09008973
Filing Dt:
01/20/1998
Title:
SYSTEM FOR EXTENDING THE AVAILABLE NUMBER OF CONFIGURATION REGISTERS
33
Patent #:
6067581
Issue Dt:
05/23/2000
Application #:
09008974
Filing Dt:
01/20/1998
Title:
METHOD FOR IDENTIFYING THE ORIGINAL SOURCE DEVICE IN A TRANSACTION REQUEST INITIATED FROM ADDRESS TRANSLATOR TO MEMORY CONTROL MODULE AND DIRECTLY PERFORMING THE TRANSACTION THEREBETWEEN
34
Patent #:
6397299
Issue Dt:
05/28/2002
Application #:
09009911
Filing Dt:
02/21/1998
Title:
A METHOD FOR CONFIGURING MEMORY TO REDUCE LATENCY
35
Patent #:
6263389
Issue Dt:
07/17/2001
Application #:
09009915
Filing Dt:
01/21/1998
Title:
APPARATUS FOR INCREASING THE NUMBER OF LOADS SUPPORTED BY A HOST BUS
36
Patent #:
6041380
Issue Dt:
03/21/2000
Application #:
09010084
Filing Dt:
01/21/1998
Title:
A METHOD FOR INCREASING THE NUMBER OF DEVICES CAPABLE OF BEING OPERABLY CONNECTED TO A HOST BUS
37
Patent #:
6075381
Issue Dt:
06/13/2000
Application #:
09010335
Filing Dt:
01/21/1998
Title:
PROGRAMMABLE LOGIC BLOCK IN AN INTEGRATED CIRCUIT
38
Patent #:
6209118
Issue Dt:
03/27/2001
Application #:
09010337
Filing Dt:
01/21/1998
Title:
METHOD FOR MODIFYING AN INTEGRATED CIRCUIT
39
Patent #:
6058450
Issue Dt:
05/02/2000
Application #:
09016055
Filing Dt:
01/30/1998
Title:
METHOD AND SYSTEM FOR APPORTIONING COMPUTER BUS BANDWITH
40
Patent #:
6128685
Issue Dt:
10/03/2000
Application #:
09025388
Filing Dt:
02/18/1998
Title:
METHOD FOR TERMINATING A PROCESSOR BUS
41
Patent #:
6122695
Issue Dt:
09/19/2000
Application #:
09025722
Filing Dt:
02/18/1998
Title:
DEVICE FOR TERMINATING A PROCESSOR BUS
42
Patent #:
6122677
Issue Dt:
09/19/2000
Application #:
09045974
Filing Dt:
03/20/1998
Title:
METHOD OF SHORTENING BOOT UP TIME IN A COMPUTER SYSTEM
43
Patent #:
6233638
Issue Dt:
05/15/2001
Application #:
09045975
Filing Dt:
03/20/1998
Title:
SYSTEM FOR CONFIGURING PEER DEVICES
44
Patent #:
6987545
Issue Dt:
01/17/2006
Application #:
09048932
Filing Dt:
03/26/1998
Title:
APPARATUS FOR ASSISTING VIDEO COMPRESSION IN A COMPUTER SYSTEM
45
Patent #:
7298425
Issue Dt:
11/20/2007
Application #:
09048933
Filing Dt:
03/26/1998
Publication #:
US20020067427
Pub Dt:
06/06/2002
Title:
METHOD FOR ASSISTING VIDEO COMPRESSION IN A COMPUTER SYSTEM
46
Patent #:
6223238
Issue Dt:
04/24/2001
Application #:
09053378
Filing Dt:
03/31/1998
Title:
METHOD OF PEER-TO-PEER MASTERING OVER A COMPUTER BUS
47
Patent #:
6073198
Issue Dt:
06/06/2000
Application #:
09053392
Filing Dt:
03/31/1998
Title:
SYSTEM FOR PEER-TO-PEER MASTERING OVER A COMPUTER BUS
48
Patent #:
6134656
Issue Dt:
10/17/2000
Application #:
09056197
Filing Dt:
04/07/1998
Title:
METHOD FOR BLOCKING BUS TRANSACTIONS DURING RESET
49
Patent #:
6108778
Issue Dt:
08/22/2000
Application #:
09056198
Filing Dt:
04/07/1998
Title:
DEVICE FOR BLOCKING BUS TRANSACTIONS DURING RESET
50
Patent #:
6360289
Issue Dt:
03/19/2002
Application #:
09059840
Filing Dt:
04/14/1998
Publication #:
US20010014920
Pub Dt:
08/16/2001
Title:
SYSTEM FOR AUTONOMOUS CONFIGURATION OF PEER DEVICES
51
Patent #:
6266770
Issue Dt:
07/24/2001
Application #:
09060099
Filing Dt:
04/14/1998
Title:
METHOD FOR AUTONOMOUS CONFIGURATION OF PEER DEVICES
52
Patent #:
6367064
Issue Dt:
04/02/2002
Application #:
09083716
Filing Dt:
05/22/1998
Title:
VERIFICATION OF SENSITIVITY LIST INTEGRITY IN A HARDWARE DESCRIPTION LANGUAGE FILE
53
Patent #:
6216224
Issue Dt:
04/10/2001
Application #:
09092460
Filing Dt:
06/05/1998
Title:
METHOD FOR READ ONLY MEMORY SHADOWING
54
Patent #:
6311245
Issue Dt:
10/30/2001
Application #:
09092585
Filing Dt:
06/05/1998
Title:
METHOD FOR TIME MULTIPLEXING A LOW-SPEED AND A HIGH-SPEED BUS OVER SHARED SIGNAL LINES OF A PHYSICAL BUS
55
Patent #:
6425041
Issue Dt:
07/23/2002
Application #:
09092586
Filing Dt:
06/05/1998
Title:
TIME-MULTIPLEXED MULTI-SPEED BUS
56
Patent #:
6330667
Issue Dt:
12/11/2001
Application #:
09092588
Filing Dt:
06/05/1998
Title:
SYSTEM FOR READ ONLY MEMORY SHADOWING CIRCUIT FOR COPYING A QUANTITY OF ROM DATA TO THE RAM PRIOR TO INITIALIZATION OF THE COMPUTER SYSTEM
57
Patent #:
6347352
Issue Dt:
02/12/2002
Application #:
09093579
Filing Dt:
06/08/1998
Title:
COMPUTER SYSTEM HAVING A PLURALITY OF BUS AGENTS COUPLED TO BUS REQUESTERS WHEREIN EACH BUS AGENT INCLUDES AN INTERNAL ARBITER THAT SELECTS ONE OF THE BUS REQUESTS
58
Patent #:
6260121
Issue Dt:
07/10/2001
Application #:
09106967
Filing Dt:
06/30/1998
Title:
METHOD FOR ADAPTIVE DECODING OF MEMORY ADDRESSES
59
Patent #:
6253276
Issue Dt:
06/26/2001
Application #:
09107782
Filing Dt:
06/30/1998
Title:
APPARATUS FOR ADAPTIVE DECODING OF MEMORY ADDRESSES
60
Patent #:
6052798
Issue Dt:
04/18/2000
Application #:
09108572
Filing Dt:
07/01/1998
Title:
SYSTEM AND METHOD FOR REMAPPING DEFECTIVE MEMORY LOCATIONS
61
Patent #:
6237007
Issue Dt:
05/22/2001
Application #:
09110083
Filing Dt:
07/02/1998
Title:
VERIFICATION OF PORT LIST INTEGRITY IN A HARDWARE DESCRIPTION LANGUAGE FILE
62
Patent #:
6349376
Issue Dt:
02/19/2002
Application #:
09111243
Filing Dt:
07/07/1998
Title:
METHOD FOR DECODING ADDRESSES
63
Patent #:
6243770
Issue Dt:
06/05/2001
Application #:
09119663
Filing Dt:
07/21/1998
Title:
METHOD FOR DETERMINING STATUS OF MULTIPLE INTERLOCKING FIFO BUFFER STRUCTURES BASED ON THE POSITION OF AT LEAST ONE POINTER OF EACH OF THE MULTIPLE FIFO BUFFERS
64
Patent #:
6088812
Issue Dt:
07/11/2000
Application #:
09119763
Filing Dt:
07/21/1998
Title:
SEQUENTIAL DATA TRANSFER METHOD
65
Patent #:
6163819
Issue Dt:
12/19/2000
Application #:
09119979
Filing Dt:
07/21/1998
Title:
SEQUENTIAL DATA TRANSFER CIRCUIT
66
Patent #:
6161153
Issue Dt:
12/12/2000
Application #:
09126942
Filing Dt:
07/30/1998
Title:
METHOD FOR SHARING DATA BUFFERS FROM A BUFFER POOL
67
Patent #:
6282589
Issue Dt:
08/28/2001
Application #:
09126978
Filing Dt:
07/30/1998
Title:
SYSTEM FOR SHARING DATA BUFFERS FROM A BUFFER POOL
68
Patent #:
6272609
Issue Dt:
08/07/2001
Application #:
09127207
Filing Dt:
07/31/1998
Title:
PIPELINED MEMORY CONTROLLER
69
Patent #:
6295592
Issue Dt:
09/25/2001
Application #:
09127282
Filing Dt:
07/31/1998
Title:
METHOD OF PROCESSING MEMORY REQUESTS IN A PIPELINED MEMORY CONTROLLER
70
Patent #:
6219764
Issue Dt:
04/17/2001
Application #:
09128403
Filing Dt:
08/03/1998
Title:
MEMORY PAGING CONTROL METHOD
71
Patent #:
6219765
Issue Dt:
04/17/2001
Application #:
09128410
Filing Dt:
08/03/1998
Title:
MEMORY PAGING CONTROL APPARATUS
72
Patent #:
6571204
Issue Dt:
05/27/2003
Application #:
09128704
Filing Dt:
08/04/1998
Title:
BUS MODELING LANGUAGE GENERATOR
73
Patent #:
6233627
Issue Dt:
05/15/2001
Application #:
09131446
Filing Dt:
08/10/1998
Title:
PROCESSOR WITH INTERNAL REGISTER FOR PERIPHERAL STATUS
74
Patent #:
6219720
Issue Dt:
04/17/2001
Application #:
09131447
Filing Dt:
08/10/1998
Title:
CORE LOGIC UNIT WITH INTERNAL REGISTER FOR PERIPHERAL STATUS
75
Patent #:
6189049
Issue Dt:
02/13/2001
Application #:
09131497
Filing Dt:
08/10/1998
Title:
METHOD FOR OPERATING PROCESSOR WITH INTERNAL REGISTER FOR PERIPHERAL STATUS
76
Patent #:
6374320
Issue Dt:
04/16/2002
Application #:
09131922
Filing Dt:
08/10/1998
Publication #:
US20020029310
Pub Dt:
03/07/2002
Title:
METHOD FOR OPERATING CORE LOGIC UNIT WITH INTERNAL REGISTER FOR PERIPHERAL STATUS
77
Patent #:
6061510
Issue Dt:
05/09/2000
Application #:
09149689
Filing Dt:
09/08/1998
Title:
LOCAL BUS INTERFACE
78
Patent #:
6145048
Issue Dt:
11/07/2000
Application #:
09153992
Filing Dt:
09/17/1998
Title:
METHOD OF PROCESSING SYSTEM MANAGEMENT INTERRUPT REQUESTS
79
Patent #:
6212592
Issue Dt:
04/03/2001
Application #:
09156182
Filing Dt:
09/17/1998
Title:
COMPUTER SYSTEM FOR PROCESSING SYSTEM MANAGEMENT INTERRUPT REQUESTS
80
Patent #:
6219755
Issue Dt:
04/17/2001
Application #:
09158169
Filing Dt:
09/21/1998
Title:
UPGRADEABLE CACHE CIRCUIT USING HIGH SPEED MULTIPLEXER
81
Patent #:
6119197
Issue Dt:
09/12/2000
Application #:
09158179
Filing Dt:
09/21/1998
Title:
METHOD FOR PROVIDING AND OPERATING UPGRADEABLE CACHE CIRCUITRY (AS AMENDED)
82
Patent #:
6304923
Issue Dt:
10/16/2001
Application #:
09172923
Filing Dt:
10/14/1998
Title:
A METHOD FOR PRIORITIZING DATA TRANSFER REQUEST BY COMPARING A LATENCY INDENTIFIER VALUE RECEIVED FROM AN I/O DEVICE WITH A PERDETERMINED RANGE OF VALUES
83
Patent #:
6266718
Issue Dt:
07/24/2001
Application #:
09172926
Filing Dt:
10/14/1998
Title:
APPARATUS FOR CONTROLLING DATA TRANSFER OPERATIONS BETWEEN A MEMORY AND DEVICES HAVING RESPECTIVE LATENCIES
84
Patent #:
6363445
Issue Dt:
03/26/2002
Application #:
09173573
Filing Dt:
10/15/1998
Title:
METHOD OF BUS ARBITRATION USING REQUESTING DEVICE BANDWIDTH AND PRIORITY RANKING
85
Patent #:
6346946
Issue Dt:
02/12/2002
Application #:
09177739
Filing Dt:
10/23/1998
Title:
GRAPHICS CONTROLLER EMBEDDED IN A CORE LOGIC UNIT
86
Patent #:
6658552
Issue Dt:
12/02/2003
Application #:
09178196
Filing Dt:
10/23/1998
Title:
PROCESSING SYSTEM WITH SEPARATE GENERAL PURPOSE EXECUTION UNIT AND DATA STRING MANIPULATION UNIT
87
Patent #:
6477623
Issue Dt:
11/05/2002
Application #:
09178207
Filing Dt:
10/23/1998
Publication #:
US20020027557
Pub Dt:
03/07/2002
Title:
METHOD FOR PROVIDING GRAPHICS CONTROLLER EMBEDDED IN A CORE LOGIC UNIT
88
Patent #:
6425056
Issue Dt:
07/23/2002
Application #:
09179236
Filing Dt:
10/26/1998
Publication #:
US20010044872
Pub Dt:
11/22/2001
Title:
METHOD FOR CONTROLLING A DIRECT MAPPED OR TWO WAY SET ASSOCIATIVE CACHE MEMORY IN A COMPUTER SYSTEM
89
Patent #:
6101612
Issue Dt:
08/08/2000
Application #:
09183627
Filing Dt:
10/30/1998
Title:
APPARATUS FOR ALIGNING CLOCK AND DATA SIGNALS RECEIVED FROM A RAM
90
Patent #:
6108795
Issue Dt:
08/22/2000
Application #:
09183781
Filing Dt:
10/30/1998
Title:
METHOD FOR ALIGNING CLOCK AND DATA SIGNALS RECEIVED FROM A RAM
91
Patent #:
6233724
Issue Dt:
05/15/2001
Application #:
09183782
Filing Dt:
10/30/1998
Title:
CIRCUIT SYNTHESIS TIME BUDGETING BASED UPON WIRELOAD INFORMATION
92
Patent #:
6233722
Issue Dt:
05/15/2001
Application #:
09189566
Filing Dt:
11/11/1998
Title:
PLACING GATES IN AN INTEGRATED CIRCUIT BASED UPON DRIVE STRENGTH
93
Patent #:
6233250
Issue Dt:
05/15/2001
Application #:
09191569
Filing Dt:
11/13/1998
Title:
SYSTEM AND METHOD FOR REDUCING LATENCY IN SOFTWARE MODEM FOR HIGH- -SPEED SYNCHRONOUS TRANSMISSION
94
Patent #:
6158758
Issue Dt:
12/12/2000
Application #:
09191571
Filing Dt:
11/13/1998
Title:
FIFTH WHEEL HITCH BUMPER
95
Patent #:
6298413
Issue Dt:
10/02/2001
Application #:
09196571
Filing Dt:
11/19/1998
Title:
APPARATUS FOR CONTROLLING REFRESH OF A MULTIBANK MEMORY DEVICE
96
Patent #:
6199138
Issue Dt:
03/06/2001
Application #:
09200622
Filing Dt:
11/30/1998
Title:
CONTROLLING A PAGING POLICY BASED ON A REQUESTOR CHARACTERISTIC
97
Patent #:
6085339
Issue Dt:
07/04/2000
Application #:
09201277
Filing Dt:
11/30/1998
Title:
SYSTEM FOR MEMORY ERROR HANDLING
98
Patent #:
6240473
Issue Dt:
05/29/2001
Application #:
09201410
Filing Dt:
11/30/1998
Title:
PROVIDING DEVICE STATUS DURING BUS RETRY OPERATIONS
99
Patent #:
6212598
Issue Dt:
04/03/2001
Application #:
09201456
Filing Dt:
11/30/1998
Title:
CONTROLLING A PAGING POLICY BASED ON A REQUESTOR CHARACTERISTIC
100
Patent #:
6324596
Issue Dt:
11/27/2001
Application #:
09201550
Filing Dt:
11/30/1998
Title:
METHOD FOR STORING DEVICE STATUS IN A TARGET DEVICE AND PROVIDING THE STORED DEVICE STATUS DURING BUS RETRY OPERATIONS
Assignor
1
MICRON ELECTRONICS, INC.
Exec Dt:
03/17/2000
Assignee
1
MICRON TECHNOLOGY, INC.
8000 S. FEDERAL WAY
BOISE, IOWA 83716
Correspondence name and address
MICRON TECHNOLOGY, INC.
WALTER D. FIELDS
PATENT DEPT., MAIL STOP 525
8000 S. FEDERAL WAY
BOISE, IDAHO 83706-9632

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