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Reel/Frame:031805/0573   Pages: 18
Recorded: 12/12/2013
Attorney Dkt #:CHEETAH #4
Conveyance: CORRECTION TO THE RECORDATION COVER SHEET OF THE INTELLECTUAL PROPERTY SECURITY AGREEMENT RECORDED AT 23129/669 ON 4/13/2009
Total properties: 21
1
Patent #:
7099179
Issue Dt:
08/29/2006
Application #:
10745178
Filing Dt:
12/22/2003
Publication #:
US20050135147
Pub Dt:
06/23/2005
Title:
CONDUCTIVE MEMORY ARRAY HAVING PAGE MODE AND BURST MODE WRITE CAPABILITY
2
Patent #:
7095644
Issue Dt:
08/22/2006
Application #:
10745264
Filing Dt:
12/22/2003
Publication #:
US20050135148
Pub Dt:
06/23/2005
Title:
CONDUCTIVE MEMORY ARRAY HAVING PAGE MODE AND BURST MODE READ CAPABILITY
3
Patent #:
7327600
Issue Dt:
02/05/2008
Application #:
11342491
Filing Dt:
01/30/2006
Publication #:
US20060164882
Pub Dt:
07/27/2006
Title:
STORAGE CONTROLLER FOR MULTIPLE CONFIGURATIONS OF VERTICAL MEMORY
4
Patent #:
7522468
Issue Dt:
04/21/2009
Application #:
11449105
Filing Dt:
06/08/2006
Publication #:
US20070286009
Pub Dt:
12/13/2007
Title:
SERIAL MEMORY INTERFACE
5
Patent #:
7619945
Issue Dt:
11/17/2009
Application #:
11506385
Filing Dt:
08/18/2006
Publication #:
US20080043559
Pub Dt:
02/21/2008
Title:
MEMORY POWER MANAGEMENT
6
Patent #:
7372753
Issue Dt:
05/13/2008
Application #:
11583676
Filing Dt:
10/19/2006
Publication #:
US20080094929
Pub Dt:
04/24/2008
Title:
TWO-CYCLE SENSING IN A TWO-TERMINAL MEMORY ARRAY HAVING LEAKAGE CURRENT
7
Patent #:
7765380
Issue Dt:
07/27/2010
Application #:
11655599
Filing Dt:
01/19/2007
Publication #:
US20080175072
Pub Dt:
07/24/2008
Title:
FAST DATA ACCESS THROUGH PAGE MANIPULATION
8
Patent #:
7813210
Issue Dt:
10/12/2010
Application #:
11893644
Filing Dt:
08/16/2007
Publication #:
US20090048819
Pub Dt:
02/19/2009
Title:
MULTIPLE-TYPE MEMORY
9
Patent #:
8164656
Issue Dt:
04/24/2012
Application #:
11897726
Filing Dt:
08/31/2007
Publication #:
US20090059036
Pub Dt:
03/05/2009
Title:
MEMORY EMULATION IN AN IMAGE CAPTURE DEVICE
10
Patent #:
7996600
Issue Dt:
08/09/2011
Application #:
11897909
Filing Dt:
08/30/2007
Publication #:
US20090063757
Pub Dt:
03/05/2009
Title:
MEMORY EMULATION IN AN ELECTRONIC ORGANIZER
11
Patent #:
8165621
Issue Dt:
04/24/2012
Application #:
11974034
Filing Dt:
10/10/2007
Publication #:
US20090098901
Pub Dt:
04/16/2009
Title:
MEMORY EMULATION IN A CELLULAR TELEPHONE
12
Patent #:
7593284
Issue Dt:
09/22/2009
Application #:
11975275
Filing Dt:
10/17/2007
Publication #:
US20090106013
Pub Dt:
04/23/2009
Title:
MEMORY EMULATION USING RESISTIVITY-SENSITIVE MEMORY
13
Patent #:
7633789
Issue Dt:
12/15/2009
Application #:
11999376
Filing Dt:
12/04/2007
Publication #:
US20090141545
Pub Dt:
06/04/2009
Title:
PLANAR THIRD DIMENSIONAL MEMORY WITH MULTI-PORT ACCESS
14
Patent #:
7796451
Issue Dt:
09/14/2010
Application #:
12001335
Filing Dt:
12/10/2007
Publication #:
US20090147598
Pub Dt:
06/11/2009
Title:
INTEGRATED CIRCUITS AND METHODS TO COMPENSATE FOR DEFECTIVE MEMORY IN MULTIPLE LAYERS OF MEMORY
15
Patent #:
7822913
Issue Dt:
10/26/2010
Application #:
12004192
Filing Dt:
12/20/2007
Publication #:
US20090164706
Pub Dt:
06/25/2009
Title:
EMULATION OF A NAND MEMORY SYSTEM
16
Patent #:
8020132
Issue Dt:
09/13/2011
Application #:
12004292
Filing Dt:
12/19/2007
Publication #:
US20080109775
Pub Dt:
05/08/2008
Title:
COMBINED MEMORIES IN INTEGRATED CIRCUITS
17
Patent #:
7751221
Issue Dt:
07/06/2010
Application #:
12004737
Filing Dt:
12/21/2007
Publication #:
US20090158918
Pub Dt:
06/25/2009
Title:
MEDIA PLAYER WITH NON-VOLATILE MEMORY
18
Patent #:
7649788
Issue Dt:
01/19/2010
Application #:
12006970
Filing Dt:
01/08/2008
Title:
BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGRATED CIRCUITS
19
Patent #:
7889571
Issue Dt:
02/15/2011
Application #:
12008212
Filing Dt:
01/09/2008
Publication #:
US20090177833
Pub Dt:
07/09/2009
Title:
BUFFERING SYSTEMS METHODS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGRATED CIRCUITS
20
Patent #:
7715244
Issue Dt:
05/11/2010
Application #:
12012641
Filing Dt:
02/05/2008
Publication #:
US20090196087
Pub Dt:
08/06/2009
Title:
NON-VOLATILE REGISTER HAVING A MEMORY ELEMENT AND REGISTER LOGIC VERTICALLY CONFIGURED ON A SUBSTRATE
21
Patent #:
7436723
Issue Dt:
10/14/2008
Application #:
12074448
Filing Dt:
03/03/2008
Publication #:
US20080159046
Pub Dt:
07/03/2008
Title:
METHOD FOR TWO-CYCLE SENSING IN A TWO-TERMINAL MEMORY ARRAY HAVING LEAKAGE CURRENT
Assignor
1
UNITY SEMICONDUCTOR CORPORATION
Exec Dt:
03/27/2009
Assignees
1
SILICON VALLEY BANK
2400 HANOVER STREET
PALO ALTO, CALIFORNIA 94304
2
GOLD HILL VENTURE LENDING 03, LP
ONE ALMADEN BLVD., SUITE 630
SUNNYVALE, CALIFORNIA 95113
Correspondence name and address
TARISA WAIN
1050 ENTERPRISE WAY, SUITE 700
SUNNYVALE, CA 94089

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