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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09376658
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Filing Dt:
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08/18/1999
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Title:
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METHOD FOR PROTECTING GATE EDGES FROM CHARGE GAIN/LOSS IN SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09619231
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Filing Dt:
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07/19/2000
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Title:
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ELIMINATION OF N+ CONTACT IMPLANT FROM FLASH TECHNOLOGIES BY REPLACEMENT WITH STANDARD DOUBLE-DIFFUSED AND N+ IMPLANTS
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09627563
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Filing Dt:
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07/28/2000
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Title:
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INTEGRATION OF AN ION IMPLANT HARD MASK STRUCTURE INTO A PROCESS FOR FABRICATING HIGH DENSITY MEMORY CELLS
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Patent #:
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Issue Dt:
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05/21/2002
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Application #:
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09670229
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Filing Dt:
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09/25/2000
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Title:
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PROCESS FOR FABRICATING SHALLOW POCKET REGIONS IN A NON-VOLATILE SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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02/12/2002
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Application #:
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09690554
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Filing Dt:
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10/17/2000
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Title:
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Word line decoding architecture in a flash memory
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Patent #:
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Issue Dt:
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12/18/2001
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Application #:
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09717550
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Filing Dt:
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11/21/2000
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Title:
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Method and system for embedded chip erase verification
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09723635
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Filing Dt:
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11/28/2000
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Title:
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SIMULTANEOUS FORMATION OF CHARGE STORAGE AND BITLINE TO WORDLINE ISOLATION
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09723653
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Filing Dt:
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11/28/2000
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Title:
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METHOD OF SIMULTANEOUS FORMATION OF BITLINE ISOLATION AND PERIPHEY OXIDE
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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09727714
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Filing Dt:
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11/28/2000
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Title:
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FLASH NVROM DEVICES WITH UV CHARGE IMMUNITY
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09795865
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Filing Dt:
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02/28/2001
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Title:
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SINGLE BIT ARRAY EDGES
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09834419
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Filing Dt:
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04/12/2001
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Title:
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SEMICONDUCTOR DEVICE HAVING GATE EDGES PROTECTED FROM CHARGE GAIN/LOSS
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09885490
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Filing Dt:
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06/20/2001
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Title:
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METHOD OF MANUFACTURING SPACER ETCH MASK FOR SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) TYPE NONVOLATILE MEMORY
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09893026
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Filing Dt:
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06/27/2001
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Publication #:
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Pub Dt:
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05/30/2002
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Title:
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PLANAR STRUCTURE FOR NON-VOLATILE MEMORY DEVICES
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09893279
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Filing Dt:
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06/27/2001
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Title:
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SOURCE DRAIN IMPLANT DURING ONO FORMATION FOR IMPROVED ISOLATION OF SONOS DEVICES
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09966702
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Filing Dt:
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09/28/2001
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Title:
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NITRIDE BARRIER LAYER FOR PROTECTION OF ONO STRUCTURE FROM TOP OXIDE LOSS IN A FABRICATION OF SONOS FLASH MEMORY
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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10006529
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Filing Dt:
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12/05/2001
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Title:
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NITRIDING PRETREATMENT OF ONO NITRIDE FOR OXIDE DEPOSITION
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Patent #:
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Issue Dt:
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03/14/2006
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Application #:
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10032248
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Filing Dt:
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12/21/2001
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Title:
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HIGH SPEED MEMORY INTERFACE SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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10069124
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Filing Dt:
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03/01/2002
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Title:
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NONVOLATILE MEMORY CIRCUIT FOR RECORDING MULTIPLE BIT INFORMATION
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Patent #:
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Issue Dt:
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04/29/2008
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Application #:
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10074884
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Filing Dt:
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02/13/2002
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Title:
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SEMICONDUCTOR TOPOGRAPHY INCLUDING A THIN OXIDE-NITRIDE STACK AND METHOD FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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10094108
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Filing Dt:
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03/08/2002
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Title:
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SONOS STRUCTURE INCLUDING A DEUTERATED OXIDE-SILICON INTERFACE AND METHOD FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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10158044
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Filing Dt:
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05/30/2002
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Title:
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NITRIDE BARRIER LAYER FOR PROTECTION OF ONO STRUCTURE FROM TOP OXIDE LOSS IN FABRICATION OF SONOS FLASH MEMORY
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Patent #:
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Issue Dt:
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12/09/2003
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Application #:
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10172670
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Filing Dt:
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06/13/2002
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Title:
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METHOD AND SYSTEM FOR PROGRAMMING A MEMORY DEVICE
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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10223195
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Filing Dt:
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08/19/2002
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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SIMULTANEOUS FORMATION OF CHARGE STORAGE AND BITLINE TO WORDLINE ISOLATION
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10230729
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Filing Dt:
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08/29/2002
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Title:
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DUMMY WORDLINE FOR ERASE AND BITLINE LEAKAGE
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Patent #:
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Issue Dt:
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03/02/2010
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Application #:
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10273184
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Filing Dt:
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10/18/2002
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Title:
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NITRIDATION OF GATE OXIDE BY LASER PROCESSING
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10308518
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Filing Dt:
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12/03/2002
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Title:
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ONO FABRICATION PROCESS FOR REDUCING OXYGEN VACANCY CONTENT IN BOTTOM OXIDE LAYER IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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10341881
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Filing Dt:
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01/14/2003
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Title:
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MEMORY DEVICE HAVING A P+ GATE AND THIN BOTTOM OXIDE AND METHOD OF ERASING SAME
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10358586
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Filing Dt:
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02/05/2003
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Title:
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ONO FABRICATION PROCESS FOR INCREASING OXYGEN CONTENT AT BOTTOM OXIDE-SUBSTRATE INTERFACE IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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10/10/2006
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Application #:
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10368696
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Filing Dt:
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02/19/2003
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Title:
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PROTECTION OF CHARGE TRAPPING DIELECTRIC FLASH MEMORY DEVICES FROM UV-INDUCED CHARGING IN BEOL PROCESSING
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Patent #:
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Issue Dt:
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11/08/2005
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Application #:
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10459576
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Filing Dt:
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06/12/2003
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Publication #:
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Pub Dt:
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12/16/2004
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Title:
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NON-VOLATILE MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/06/2005
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Application #:
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10618514
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Filing Dt:
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07/11/2003
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Title:
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METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING TRIPLE LDD STRUCTURE AND LOWER GATE RESISTANCE FORMED WITH A SINGLE IMPLANT PROCESS
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10653050
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Filing Dt:
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08/29/2003
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Title:
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METHOD AND SYSTEM FOR PROGRAMMING A MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/28/2005
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Application #:
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10658506
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Filing Dt:
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09/09/2003
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Publication #:
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Pub Dt:
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07/15/2004
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Title:
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MEMORY DEVICE HAVING HIGH WORK FUNCTION GATE AND METHOD OF ERASING SAME
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Patent #:
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Issue Dt:
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10/25/2005
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Application #:
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10679774
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Filing Dt:
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10/06/2003
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Title:
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FLASH MEMORY DEVICE AND METHOD OF FABRICATION THEREOF INCLUDING A BOTTOM OXIDE LAYER WITH TWO REGIONS WITH DIFFERENT CONCENTRATIONS OF NITROGEN
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Patent #:
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Issue Dt:
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06/07/2005
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Application #:
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10684890
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Filing Dt:
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10/14/2003
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Title:
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NON VOLATILE CHARGE TRAPPING DIELECTRIC MEMORY CELL STRUCTURE WITH GATE HOLE INJECTION ERASE
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10716209
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Filing Dt:
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11/18/2003
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Title:
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TIGHTLY SPACED GATE FORMATION THROUGH DAMASCENE PROCESS
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Patent #:
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Issue Dt:
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05/09/2006
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Application #:
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10740205
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Filing Dt:
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12/18/2003
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Title:
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SONOS STRUCTURE INCLUDING A DEUTERATED OXIDE-SILICON INTERFACE AND METHOD FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10754948
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Filing Dt:
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01/08/2004
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Title:
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INTEGRATED ONO PROCESSING FOR SEMICONDUCTOR DEVICES USING IN-SITU STEAM GENERATION (ISSG) PROCESS
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Patent #:
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Issue Dt:
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10/25/2005
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Application #:
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10755740
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Filing Dt:
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01/12/2004
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Publication #:
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Pub Dt:
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07/14/2005
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Title:
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POCKET IMPLANT FOR COMPLEMENTARY BIT DISTURB IMPROVEMENT AND CHARGING IMPROVEMENT OF SONOS MEMORY CELL
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Patent #:
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Issue Dt:
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04/11/2006
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Application #:
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10795890
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Filing Dt:
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03/08/2004
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Title:
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SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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08/15/2006
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Application #:
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10861437
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Filing Dt:
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06/03/2004
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Title:
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UV-BLOCKING ETCH STOP LAYER FOR REDUCING UV-INDUCED CHARGING OF CHARGE STORAGE LAYER IN MEMORY DEVICES IN BEOL PROCESSING
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Issue Dt:
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02/07/2006
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10878091
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06/28/2004
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Publication #:
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Pub Dt:
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11/25/2004
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Title:
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MEMORY DEVICE HAVING A P+ GATE AND THIN BOTTOM OXIDE AND METHOD OF ERASING SAME
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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10889424
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Filing Dt:
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07/12/2004
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Title:
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ONO FABRICATION PROCESS FOR REDUCING OXYGEN VACANCY CONTENT IN BOTTOM OXIDE LAYER IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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04/08/2014
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Application #:
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10927692
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Filing Dt:
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08/27/2004
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Title:
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MEMORY DEVICES CONTAINING A HIGH-K DIELECTRIC LAYER
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Patent #:
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12/19/2006
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10928582
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08/27/2004
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Title:
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SONOS MEMORY WITH INVERSION BIT-LINES
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07/03/2007
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11063560
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02/24/2005
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Title:
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NON-VOLATILE MEMORY DEVICE WITH INCREASED RELIABILITY
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04/22/2008
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11073178
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03/04/2005
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Title:
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FLYBACK CAPACITOR LEVEL SHIFTER FEEDBACK REGULATION FOR NEGATIVE PUMPS
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12/25/2007
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11101783
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04/07/2005
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Publication #:
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Pub Dt:
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10/12/2006
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Title:
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SPLIT GATE MULTI-BIT MEMORY CELL
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06/19/2007
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11113507
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04/25/2005
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Title:
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RADICAL OXIDATION FOR BITLINE OXIDE OF SONOS
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08/01/2006
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11120690
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05/02/2005
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Title:
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A SEMICONDUCTOR DEVICE HAVING TRIPLE LDD STRUCTURE AND LOWER GATE RESISTANCE FORMED WITH A SINGLE IMPLANT PROCESS
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11/27/2007
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11147208
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06/08/2005
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Title:
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INTERLAYER DIELECTRIC FOR CHARGE LOSS IMPROVEMENT
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03/13/2012
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11189875
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07/27/2005
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Title:
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METHOD FOR FORMING A SEMICONDUCTING LAYER WITH IMPROVED GAP FILLING PROPERTIES
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10/23/2007
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11194449
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08/02/2005
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Title:
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BACK-TO-BACK NPN/PNP PROTECTION DIODES
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11/04/2008
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11196434
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08/04/2005
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02/08/2007
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Title:
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SONOS MEMORY CELL HAVING HIGH-K DIELECTRIC
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11/13/2007
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11229664
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09/20/2005
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03/22/2007
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FLASH MEMORY PROGRAMMING USING AN INDICATION BIT TO INTERPRET STATE
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01/20/2009
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11237591
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09/27/2005
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04/13/2006
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SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
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12/09/2008
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11268025
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11/07/2005
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METHOD OF INCREASING ERASE SPEED IN MEMORY ARRAYS
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02/21/2012
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11469164
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08/31/2006
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05/29/2008
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MEMORY SYSTEM WITH PROTECTION LAYER TO COVER THE MEMORY GATE STACK AND METHODS FOR FORMING SAME
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05/06/2008
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11538404
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10/03/2006
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04/03/2008
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Title:
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DUAL BIT FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
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03/27/2012
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11539984
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10/10/2006
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04/10/2008
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MEMORY CELL SYSTEM WITH CHARGE TRAP
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12/30/2008
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11566767
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12/05/2006
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06/05/2008
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Title:
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MULTIPLEXER CIRCUIT
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03/10/2009
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11595639
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11/10/2006
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03/15/2007
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SONOS MEMORY WITH INVERSION BIT-LINES
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07/06/2010
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11612265
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12/18/2006
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06/19/2008
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STRAPPING CONTACT FOR CHARGE PROTECTION
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06/29/2010
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11756832
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06/01/2007
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POLARITY CONVERSION CIRCUIT
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03/02/2010
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11801543
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Filing Dt:
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05/10/2007
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Title:
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CHARGE PUMP CONTROL CIRCUIT AND METHOD
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11811958
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Filing Dt:
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06/13/2007
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Publication #:
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Pub Dt:
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07/16/2009
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Title:
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Oxide-nitride-oxide stack having multiple oxynitride layers
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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11836683
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Filing Dt:
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08/09/2007
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Title:
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OXIDE FORMATION IN A PLASMA PROCESS
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Patent #:
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Issue Dt:
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08/11/2009
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Application #:
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11855704
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Filing Dt:
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09/14/2007
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Title:
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BACK-TO-BACK NPN/PNP PROTECTION DIODES
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Patent #:
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Issue Dt:
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12/21/2010
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Application #:
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11901751
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Filing Dt:
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09/19/2007
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Title:
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CHARGE PUMP
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Patent #:
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Issue Dt:
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04/27/2010
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Application #:
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11904112
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Filing Dt:
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09/25/2007
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Publication #:
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Pub Dt:
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03/26/2009
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Title:
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METHOD AND APPARATUS FOR REDUCTION OF BIT-LINE DISTURB AND SOFT-ERASE IN A TRAPPED-CHARGE MEMORY
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Patent #:
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Issue Dt:
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02/01/2011
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Application #:
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11904470
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Filing Dt:
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09/26/2007
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Publication #:
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Pub Dt:
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11/27/2008
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Title:
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NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING <100> CRYSTAL PLANE CHANNEL ORIENTATION
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Patent #:
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Issue Dt:
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09/17/2013
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Application #:
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11904474
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Filing Dt:
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09/26/2007
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Publication #:
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Pub Dt:
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01/22/2009
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Title:
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DEUTERATED FILM ENCAPSULATION OF NONVOLATILE CHARGE TRAP MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/25/2014
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Application #:
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11904475
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Filing Dt:
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09/26/2007
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Publication #:
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Pub Dt:
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11/27/2008
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Title:
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NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A DEUTERATED LAYER IN A MULTI-LAYER CHARGE-TRAPPING REGION
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Patent #:
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Issue Dt:
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12/24/2013
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Application #:
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11904506
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Filing Dt:
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09/26/2007
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Publication #:
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Pub Dt:
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11/27/2008
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Title:
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SONOS ONO STACK SCALING
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Patent #:
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Issue Dt:
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03/02/2010
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Application #:
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11904513
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Filing Dt:
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09/26/2007
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Publication #:
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Pub Dt:
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11/27/2008
| | | | |
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Title:
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SINGLE-WAFER PROCESS FOR FABRICATING A NONVOLATILE CHARGE TRAP MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/14/2010
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Application #:
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11904642
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Filing Dt:
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09/28/2007
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Title:
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CURRENT REFERENCE SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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03/08/2011
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Application #:
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11966631
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Filing Dt:
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12/28/2007
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Title:
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METHOD AND APPARATUS FOR REDUCTION OF BIT-LINE DISTURB AND SOFT-ERASE IN A TRAPPED-CHARGE MEMORY
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Patent #:
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Issue Dt:
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10/26/2010
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Application #:
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11973696
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Filing Dt:
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10/09/2007
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Title:
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ADAPTIVE CURRENT SENSE AMPLIFIER WITH DIRECT ARRAY ACCESS CAPABILITY
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Patent #:
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Issue Dt:
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07/10/2012
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Application #:
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11975967
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Filing Dt:
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10/22/2007
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Title:
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HIGH PRECISION CURRENT REFERENCE USING OFFSET PTAT CORRECTION
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Patent #:
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Issue Dt:
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10/26/2010
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Application #:
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11985206
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Filing Dt:
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11/14/2007
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Title:
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LOW IMPEDANCE COLUMN MULTIPLEXER CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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03/01/2011
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Application #:
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12005803
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Filing Dt:
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12/27/2007
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Title:
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TRAPPED-CHARGE NON-VOLATILE MEMORY WITH UNIFORM MULTILEVEL PROGRAMMING
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Patent #:
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Issue Dt:
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01/28/2014
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Application #:
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12005813
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Filing Dt:
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12/27/2007
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Publication #:
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Pub Dt:
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02/05/2009
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Title:
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NITRIDATION OXIDATION OF TUNNELING LAYER FOR IMPROVED SONOS SPEED AND RETENTION
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Patent #:
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Issue Dt:
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11/29/2011
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Application #:
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12006961
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Filing Dt:
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01/08/2008
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Title:
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OXYNITRIDE BILAYER FORMED USING A PRECURSOR INDUCING A HIGH CHARGE TRAP DENSITY IN A TOP LAYER OF THE BILAYER
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12030644
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Filing Dt:
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02/13/2008
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Publication #:
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Pub Dt:
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06/18/2009
| | | | |
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Title:
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NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A HIGH DIELECTRIC CONSTANT BLOCKING REGION
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Patent #:
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Issue Dt:
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01/11/2011
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Application #:
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12046073
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Filing Dt:
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03/11/2008
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Title:
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SEMICONDUCTOR TOPOGRAPHY INCLUDING A THIN OXIDE-NITRIDE STACK AND METHOD FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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03/31/2015
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Application #:
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12049089
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Filing Dt:
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03/14/2008
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Publication #:
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Pub Dt:
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09/18/2008
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Title:
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SEMICONDUCTOR DEVICE WITH ONO FILM
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Patent #:
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Issue Dt:
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04/27/2010
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Application #:
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12054081
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Filing Dt:
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03/24/2008
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Publication #:
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Pub Dt:
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07/17/2008
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Title:
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DUAL BIT FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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05/04/2010
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Application #:
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12059155
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Filing Dt:
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03/31/2008
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Title:
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HIGH SPEED CIRCUIT AND A METHOD TO TEST MEMORY ADDRESS UNIQUENESS
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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12075552
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Filing Dt:
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03/12/2008
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Title:
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MEMORY TEST AND SETUP METHOD
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Patent #:
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Issue Dt:
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01/03/2012
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Application #:
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12080166
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Filing Dt:
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03/31/2008
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Publication #:
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Pub Dt:
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10/01/2009
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Title:
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SEQUENTIAL DEPOSITION AND ANNEAL OF A DIELECTIC LAYER IN A CHARGE TRAPPING MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/21/2010
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Application #:
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12080175
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Filing Dt:
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03/31/2008
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Publication #:
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Pub Dt:
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10/01/2009
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Title:
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PLASMA OXIDATION OF A MEMORY LAYER TO FORM A BLOCKING LAYER IN NON-VOLATILE CHARGE TRAP MEMORY DEVICES
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Patent #:
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Issue Dt:
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04/20/2010
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Application #:
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12107538
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Filing Dt:
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04/22/2008
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Title:
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FLYBACK CAPACITOR LEVEL SHIFTER FEEDBACK REGULATION FOR NEGATIVE PUMPS
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Patent #:
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Issue Dt:
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10/09/2012
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Application #:
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12124855
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Filing Dt:
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05/21/2008
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Pub Dt:
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11/27/2008
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Title:
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RADICAL OXIDATION PROCESS FOR FABRICATING A NONVOLATILE CHARGE TRAP MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/10/2012
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Application #:
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12125864
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Filing Dt:
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05/22/2008
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Pub Dt:
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11/27/2008
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Title:
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INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES
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Patent #:
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08/09/2011
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Application #:
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12151282
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Filing Dt:
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05/05/2008
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Title:
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POWER SUPPLY TRACKING SINGLE ENDED SENSING SCHEME FOR SONOS MEMORIES
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Patent #:
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Issue Dt:
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11/22/2011
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Application #:
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12152518
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Filing Dt:
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05/13/2008
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Title:
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MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE
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08/31/2010
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12154547
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05/22/2008
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03/26/2009
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Title:
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PROGRAMMABLE CSONOS LOGIC ELEMENT
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02/01/2011
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12154585
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05/22/2008
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Pub Dt:
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12/04/2008
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Title:
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SENSE TRANSISTOR PROTECTION FOR MEMORY PROGRAMMING
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03/27/2012
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12185747
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08/04/2008
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12/04/2008
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INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES
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03/25/2014
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12185751
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08/04/2008
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12/04/2008
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INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES
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