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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	020385/0574			Pages:	7
		Recorded:	01/17/2008
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 35

Patent #:	6746577	Issue Dt:	06/08/2004	Application #:	09465880	Filing Dt:	12/16/1999
Title:	METHOD AND APPARATUS FOR THICKNESS CONTROL AND REPRODUCIBILITY OF DIELECTRIC FILM DEPOSITION

Patent #:	6642743	Issue Dt:	11/04/2003	Application #:	10072458	Filing Dt:	02/07/2002
Publication #:	US20020114200	Pub Dt:	08/22/2002
Title:	SYSTEM FOR RAPID CONFIGURATION OF A PROGRAMMABLE LOGIC DEVICE

Patent #:	6646465	Issue Dt:	11/11/2003	Application #:	10072461	Filing Dt:	02/07/2002
Publication #:	US20020113618	Pub Dt:	08/22/2002
Title:	PROGRAMMABLE LOGIC DEVICE INCLUDING BI-DIRECTIONAL SHIFT REGISTER

Patent #:	6624771	Issue Dt:	09/23/2003	Application #:	10145390	Filing Dt:	05/14/2002
Publication #:	US20020175703	Pub Dt:	11/28/2002
Title:	CONCURRENT LOGIC OPERATIONS USING DECODER CIRCUITRY OF A LOOK-UP TABLE

Patent #:	7038489	Issue Dt:	05/02/2006	Application #:	10172355	Filing Dt:	06/14/2002
Publication #:	US20020194449	Pub Dt:	12/19/2002
Title:	METHOD FOR SHARING CONFIGURATION DATA FOR HIGH LOGIC DENSITY ON CHIP

Patent #:	6788104	Issue Dt:	09/07/2004	Application #:	10186346	Filing Dt:	06/28/2002
Publication #:	US20030001614	Pub Dt:	01/02/2003
Title:	FIELD PROGRAMMABLE LOGIC DEVICE WITH EFFICIENT MEMORY UTILIZATION

Patent #:	6794906	Issue Dt:	09/21/2004	Application #:	10269166	Filing Dt:	10/10/2002
Publication #:	US20040070424	Pub Dt:	04/15/2004
Title:	DECODER SCHEME FOR MAKING LARGE SIZE DECODER

Patent #:	7206919	Issue Dt:	04/17/2007	Application #:	10319436	Filing Dt:	12/13/2002
Publication #:	US20030145193	Pub Dt:	07/31/2003
Title:	RAPID PARTIAL CONFIGURATION OF RECONFIGURABLE DEVICES

Patent #:	7157936	Issue Dt:	01/02/2007	Application #:	10347139	Filing Dt:	01/17/2003
Publication #:	US20030172363	Pub Dt:	09/11/2003
Title:	UTILIZATION OF UNUSED IO BLOCK FOR CORE LOGIC FUNCTIONS

Patent #:	6879185	Issue Dt:	04/12/2005	Application #:	10407801	Filing Dt:	04/04/2003
Publication #:	US20030218480	Pub Dt:	11/27/2003
Title:	LOW POWER CLOCK DISTRIBUTION SCHEME

Patent #:	7154299	Issue Dt:	12/26/2006	Application #:	10407802	Filing Dt:	04/04/2003
Publication #:	US20030214321	Pub Dt:	11/20/2003
Title:	ARCHITECTURE FOR PROGRAMMABLE LOGIC DEVICE

Patent #:	7167404	Issue Dt:	01/23/2007	Application #:	10436895	Filing Dt:	05/13/2003
Publication #:	US20040015758	Pub Dt:	01/22/2004
Title:	METHOD AND DEVICE FOR TESTING CONFIGURATION MEMORY CELLS IN PROGRAMMABLE LOGIC DEVICES (PLDS)

Patent #:	6864714	Issue Dt:	03/08/2005	Application #:	10460040	Filing Dt:	06/10/2003
Publication #:	US20030234667	Pub Dt:	12/25/2003
Title:	PLDS PROVIDING REDUCED DELAYS IN CASCADE CHAIN CIRCUITS

Patent #:	6888374	Issue Dt:	05/03/2005	Application #:	10464420	Filing Dt:	06/17/2003
Publication #:	US20040036499	Pub Dt:	02/26/2004
Title:	FPGA PERIPHERAL ROUTING WITH SYMMETRIC EDGE TERMINATION AT FPGA BOUNDARIES

Patent #:	6873182	Issue Dt:	03/29/2005	Application #:	10608854	Filing Dt:	06/27/2003
Publication #:	US20040070422	Pub Dt:	04/15/2004
Title:	PROGRAMMABLE LOGIC DEVICES HAVING ENHANCED CASCADE FUNCTIONS TO PROVIDE INCREASED FLEXIBILITY

Patent #:	7350134	Issue Dt:	03/25/2008	Application #:	10667199	Filing Dt:	09/18/2003
Publication #:	US20040153923	Pub Dt:	08/05/2004
Title:	METHOD AND APPARATUS OF RELOADING ERRONEOUS CONFIGURATION DATA FRAMES DURING CONFIGURATION OF PROGRAMMABLE LOGIC DEVICES

Patent #:	7124392	Issue Dt:	10/17/2006	Application #:	10675908	Filing Dt:	09/29/2003
Publication #:	US20040133869	Pub Dt:	07/08/2004
Title:	MAPPING OF PROGRAMMABLE LOGIC DEVICES

Patent #:	6894541	Issue Dt:	05/17/2005	Application #:	10684076	Filing Dt:	10/10/2003
Publication #:	US20040130353	Pub Dt:	07/08/2004
Title:	SENSE AMPLIFIER WITH FEEDBACK-CONTROLLED BITLINE ACCESS

Patent #:	7030648	Issue Dt:	04/18/2006	Application #:	10739395	Filing Dt:	12/18/2003
Publication #:	US20040178821	Pub Dt:	09/16/2004
Title:	HIGH PERFORMANCE INTERCONNECT ARCHITECTURE FOR FIELD PROGRAMMABLE GATE ARRAYS

Patent #:	7078932	Issue Dt:	07/18/2006	Application #:	10830854	Filing Dt:	04/23/2004
Publication #:	US20050035782	Pub Dt:	02/17/2005
Title:	PROGRAMMABLE LOGIC DEVICE WITH REDUCED POWER CONSUMPTION

Patent #:	7191427	Issue Dt:	03/13/2007	Application #:	10830862	Filing Dt:	04/23/2004
Publication #:	US20050039157	Pub Dt:	02/17/2005
Title:	METHOD FOR MAPPING A LOGIC CIRCUIT TO A PROGRAMMABLE LOOK UP TABLE (LUT)

Patent #:	7157935	Issue Dt:	01/02/2007	Application #:	10954981	Filing Dt:	09/30/2004
Publication #:	US20050127943	Pub Dt:	06/16/2005
Title:	METHOD AND DEVICE FOR CONFIGURATION OF PLDS

Patent #:	7606969	Issue Dt:	10/20/2009	Application #:	11005247	Filing Dt:	12/06/2004
Publication #:	US20050172070	Pub Dt:	08/04/2005
Title:	PROGRAMMABLE LOGIC DEVICES

Patent #:	7415681	Issue Dt:	08/19/2008	Application #:	11025785	Filing Dt:	12/29/2004
Publication #:	US20050156626	Pub Dt:	07/21/2005
Title:	OPTIMAL MAPPING OF LUT BASED FPGA

Patent #:	7430726	Issue Dt:	09/30/2008	Application #:	11027292	Filing Dt:	12/30/2004
Publication #:	US20050177808	Pub Dt:	08/11/2005
Title:	AN IMPROVED SYSTEM FOR DELAY REDUCTION DURING TECHNOLOGY MAPPING IN FPGA

Patent #:	7271616	Issue Dt:	09/18/2007	Application #:	11190509	Filing Dt:	07/26/2005
Publication #:	US20060022700	Pub Dt:	02/02/2006
Title:	FPGA-BASED DIGITAL CIRCUIT FOR REDUCING READBACK TIME

Patent #:	8112466	Issue Dt:	02/07/2012	Application #:	11238123	Filing Dt:	09/28/2005
Publication #:	US20060075012	Pub Dt:	04/06/2006
Title:	FIELD PROGRAMMABLE GATE ARRAY

Patent #:	7196942	Issue Dt:	03/27/2007	Application #:	11254558	Filing Dt:	10/20/2005
Publication #:	US20060120141	Pub Dt:	06/08/2006
Title:	CONFIGURATION MEMORY STRUCTURE

Patent #:	7307452	Issue Dt:	12/11/2007	Application #:	11258616	Filing Dt:	10/25/2005
Publication #:	US20060139055	Pub Dt:	06/29/2006
Title:	INTERCONNECT STRUCTURE ENABLING INDIRECT ROUTING IN PROGRAMMABLE LOGIC

Patent #:	7750673	Issue Dt:	07/06/2010	Application #:	11261420	Filing Dt:	10/27/2005
Publication #:	US20060087342	Pub Dt:	04/27/2006
Title:	INTERCONNECT STRUCTURE AND METHOD IN PROGRAMMABLE DEVICES

Patent #:	7372296	Issue Dt:	05/13/2008	Application #:	11263386	Filing Dt:	10/31/2005
Publication #:	US20060091903	Pub Dt:	05/04/2006
Title:	CONFIGURABLE LOGIC DEVICE PROVIDING ENHANCED FLEXIBILITY, SCALABILITY AND PROVIDING AREA EFFICIENT IMPLEMENTATION OF ARITHMETIC OPERATION ON N-BIT VARIABLES

Patent #:	7755387	Issue Dt:	07/13/2010	Application #:	11264674	Filing Dt:	11/01/2005
Publication #:	US20060119388	Pub Dt:	06/08/2006
Title:	FPGA HAVING A DIRECT ROUTING STRUCTURE

Patent #:	7477070	Issue Dt:	01/13/2009	Application #:	11294645	Filing Dt:	12/05/2005
Publication #:	US20060255833	Pub Dt:	11/16/2006
Title:	RAPID INTERCONNECT AND LOGIC TESTING OF FPGA DEVICE

Patent #:	7779318	Issue Dt:	08/17/2010	Application #:	11318347	Filing Dt:	12/23/2005
Publication #:	US20070011539	Pub Dt:	01/11/2007
Title:	SELF TEST STRUCTURE FOR INTERCONNECT AND LOGIC ELEMENT TESTING IN PROGRAMMABLE DEVICES

Patent #:	7676782	Issue Dt:	03/09/2010	Application #:	11319015	Filing Dt:	12/27/2005
Publication #:	US20060190906	Pub Dt:	08/24/2006
Title:	EFFICIENT METHOD FOR MAPPING A LOGIC DESIGN ON FIELD PROGRAMMABLE GATE ARRAYS

Assignor

STMICROELECTRONICS PVT, LTD.

Exec Dt:

11/12/2007

Assignee

STMICROELECTRONICS NV

39 CHEMIN DU CHAMP-DE-FILLES

1228 PALN-LES-QUATES

GENEVA, SWITZERLAND

Correspondence name and address
	SADLER, BREEN, MORASCH & COLBY, PS
	422 W. RIVERSIDE AVE,. SUITE 424
	SPOKANE, WA 99201

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