Total properties:
13
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09097874
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Filing Dt:
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06/15/1998
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Title:
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FUNCTIONAL VERIFICATION OF INTEGRATED CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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09627347
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Filing Dt:
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07/28/2000
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Title:
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FUNCTIONAL VERIFICATION OF INTEGRATED CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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09738259
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Filing Dt:
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12/14/2000
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Publication #:
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Pub Dt:
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08/22/2002
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Title:
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TRACING THE CHANGE OF STATE OF A SIGNAL IN A FUNCTIONAL VERIFICATION SYSTEM
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Patent #:
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Issue Dt:
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02/10/2004
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Application #:
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09738260
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Filing Dt:
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12/14/2000
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Publication #:
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Pub Dt:
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02/27/2003
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Title:
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FUNCTIONAL VERIFICATION SYSTEM
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09738263
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Filing Dt:
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12/14/2000
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Publication #:
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Pub Dt:
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08/22/2002
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Title:
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TRACING DIFFERENT STATES REACHED BY A SIGNAL IN A FUNCTIONAL VERIFICATION SYSTEM
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Patent #:
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Issue Dt:
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09/23/2003
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Application #:
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09738272
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Filing Dt:
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12/14/2000
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Publication #:
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Pub Dt:
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08/29/2002
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Title:
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RUN-TIME CONTROLLER IN A FUNCTIONAL VERIFICATION SYSTEM
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09738273
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Filing Dt:
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12/14/2000
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Publication #:
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Pub Dt:
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08/15/2002
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Title:
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FUNCTIONAL VERIFICATION OF BOTH CYCLE-BASED AND NON-CYCLE BASED DESIGNS
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Patent #:
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Issue Dt:
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03/24/2009
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Application #:
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11307130
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Filing Dt:
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01/25/2006
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Publication #:
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Pub Dt:
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12/07/2006
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Title:
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A COMPACT PROCESSOR ELEMENT FOR A SCALABLE DIGITAL LOGIC VERIFICATION AND EMULATION SYSTEM
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Patent #:
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Issue Dt:
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06/16/2009
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Application #:
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11307198
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Filing Dt:
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01/26/2006
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Publication #:
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Pub Dt:
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12/07/2006
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Title:
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A SCALABLE SYSTEM FOR SIMULATION AND EMULATION OF ELECTRONIC CIRCUITS USING ASYMMETRICAL EVALUATION AND CANVASSING INSTRUCTION PROCESSORS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11307206
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Filing Dt:
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01/26/2006
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Publication #:
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Pub Dt:
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12/07/2006
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Title:
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A reconfigurable system for verification of electronic circuits using high-speed serial links to connect asymmetrical evaluation and canvassing instruction processors
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11379046
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Filing Dt:
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04/17/2006
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Publication #:
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Pub Dt:
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12/07/2006
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Title:
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A system and method for simulation of electronic circuits generating clocks and delaying the execution of instructions in a plurality of processors
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11427945
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Filing Dt:
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06/30/2006
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Publication #:
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Pub Dt:
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02/22/2007
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Title:
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A system and method for compiling a description of an electronic circuit to instructions adapted to execute on a plurality of processors
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Patent #:
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Issue Dt:
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01/22/2013
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Application #:
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11766017
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Filing Dt:
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06/20/2007
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Publication #:
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Pub Dt:
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12/20/2007
| | | | |
Title:
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METHOD FOR DELAY IMMUNE AND ACCELERATED EVALUATION OF DIGITAL CIRCUITS BY COMPILING ASYNCHRONOUS COMPLETION HANDSHAKING MEANS
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