Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 037482/0576 | |
| Pages: | 11 |
| | Recorded: | 01/13/2016 | | |
| Conveyance: | MERGER (SEE DOCUMENT FOR DETAILS). |
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Total properties:
5
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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09072879
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Filing Dt:
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05/05/1998
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Title:
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DOUBLE GATE DRAM MEMORY CELL
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Patent #:
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Issue Dt:
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12/09/2003
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Application #:
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09546747
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Filing Dt:
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04/11/2000
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Title:
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RANDOM ACCESS MEMORY CELL HAVING DOUBLE-GATE ACCESS TRANSISTOR FOR REDUCED LEAKAGE CURRENT
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Patent #:
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Issue Dt:
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12/09/2003
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Application #:
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10350653
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Filing Dt:
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01/24/2003
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Title:
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RANDOM ACCESS MEMORY CELL HAVING REDUCED LEAKAGE CURRENT
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10675042
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Filing Dt:
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09/29/2003
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Title:
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RANDOM ACCESS MEMORY CELL HAVING REDUCED CURRENT LEAKAGE AND HAVING A PASS TRANSISTOR CONTROL GATE FORMED IN A TRENCH
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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10832038
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Filing Dt:
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04/26/2004
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Publication #:
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Pub Dt:
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10/21/2004
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Title:
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SEMICONDUCTOR MEMORY DEVICE INCLUDING A DOUBLE-GATE DYNAMIC RANDOM ACCESS MEMORY CELL HAVING REDUCED CURRENT LEAKAGE
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Assignee
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| 2711 CENTERVILLE RD |
| SUITE 400 |
| WILMINGTON, DELAWARE 19808 |
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Correspondence name and address
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FOLEY & LARDNER LLP
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150 EAST GILMAN ST.
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VEREX PLAZA
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MADISON, WI 53703
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