Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 021096/0593 | |
| Pages: | 7 |
| | Recorded: | 06/16/2008 | | |
| Attorney Dkt #: | 135-G001 (TTC NAME CHG) |
| Conveyance: | CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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02/27/1996
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Application #:
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08252284
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Filing Dt:
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05/31/1994
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Title:
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REDUNDANCY SCHEME FOR MEMORY CIRCUITS
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Patent #:
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Issue Dt:
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09/26/1995
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Application #:
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08297723
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Filing Dt:
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08/26/1994
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Title:
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FAST VOLTAGE EQUILIBRATION OF COMPLEMENTARY DATA LINES FOLLOWING WRITE CYCLE IN MEMORY CIRCUITS
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Patent #:
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Issue Dt:
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12/17/1996
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Application #:
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08321390
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Filing Dt:
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10/11/1994
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Title:
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HIGH SPEED LOW POWER SENSE AMPLIFIER
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Patent #:
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Issue Dt:
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08/13/1996
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Application #:
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08438148
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Filing Dt:
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05/09/1995
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Title:
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FAST VOLTAGE EQUILIBRATION OF DIFFERENTIAL DATA LINES
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Assignee
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| TWO EMBARCADERO CENTER, 8TH FLOOR |
| SAN FRANCISCO, CALIFORNIA 94111 |
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Correspondence name and address
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ANDREW C. GRAHAM
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7600B N. CAPITAL OF TEXAS HWY.
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SUITE 350
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AUSTIN, TX 78731
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