Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 017105/0594 | |
| Pages: | 9 |
| | Recorded: | 02/02/2006 | | |
| Attorney Dkt #: | 6854-12 |
| Conveyance: | SECURITY AGREEMENT |
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Total properties:
10
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Patent #:
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Issue Dt:
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01/31/2006
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Application #:
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10118242
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Filing Dt:
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04/09/2002
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Publication #:
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Pub Dt:
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10/09/2003
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Title:
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APPARATUS AND METHOD FOR HANDLING OF MULTI-LEVEL CIRCUIT DESIGN DATA
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Patent #:
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Issue Dt:
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10/02/2007
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Application #:
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10172996
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Filing Dt:
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06/18/2002
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Publication #:
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Pub Dt:
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12/18/2003
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Title:
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METHOD FOR DETECTING BUS CONTENTION FROM RTL DESCRIPTION
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Patent #:
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Issue Dt:
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04/05/2005
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Application #:
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10217535
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Filing Dt:
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08/14/2002
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Publication #:
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Pub Dt:
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02/19/2004
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Title:
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METHOD FOR DETERMINING FAULT COVERAGE FROM RTL DESCRIPTION
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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10631755
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Filing Dt:
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08/01/2003
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Publication #:
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Pub Dt:
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02/03/2005
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Title:
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IDENTIFICATION AND IMPLEMENTATION OF CLOCK GATING IN THE DESIGN OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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10695803
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Filing Dt:
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10/30/2003
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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METHOD FOR CLOCK SYNCHRONIZATION VALIDATION IN INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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03/25/2008
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Application #:
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10711493
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Filing Dt:
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09/21/2004
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Publication #:
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Pub Dt:
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03/23/2006
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Title:
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A METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR GENERATING AND VERIFYING ISOLATION LOGIC MODULES IN DESIGN OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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12/19/2006
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Application #:
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10711971
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Filing Dt:
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10/15/2004
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Publication #:
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Pub Dt:
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04/20/2006
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Title:
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A METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR AUTOMATIC INSERTION AND CORRECTNESS VERIFICATION OF LEVEL SHIFTERS IN INTEGRATED CIRCUITS WITH MULTIPLE VOLTAGE DOMAINS
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Patent #:
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Issue Dt:
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05/08/2007
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Application #:
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10783091
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Filing Dt:
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02/23/2004
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Publication #:
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Pub Dt:
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05/19/2005
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Title:
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PATTERN RECOGNITION IN AN INTEGRATED CIRCUIT DESIGN
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10906571
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Filing Dt:
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02/24/2005
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Publication #:
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Pub Dt:
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08/24/2006
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Title:
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A Method for Automatic Recognition of Handshake Data Exchange at Clock-Domain Crossing in Integrated Circuit Design
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Patent #:
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Issue Dt:
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09/02/2008
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Application #:
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11260225
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Filing Dt:
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10/28/2005
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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CHIP DEVELOPMENT SYSTEM ENABLED FOR THE HANDLING OF MULTI-LEVEL CIRCUIT DESIGN DATA
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Assignee
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| 525 UNIVERSITY AVENUE |
| SUITE 700 |
| PALO ALTO, CALIFORNIA 94301 |
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Correspondence name and address
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JEFFREY A. O'CONNELL, ESQ.
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ONE MARITIME PLAZA
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18TH FLOOR
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SAN FRANCISCO, CA 94111
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