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03/27/2007
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11029740
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01/04/2005
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Pub Dt:
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07/06/2006
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Title:
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CMOS TRANSISTOR JUNCTION REGIONS FORMED BY A CVD ETCHING AND DEPOSITION SEQUENCE
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01/20/2009
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11643523
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12/21/2006
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Publication #:
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Pub Dt:
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05/10/2007
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Title:
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CMOS TRANSISTOR JUNCTION REGIONS FORMED BY A CVD ETCHING AND DEPOSITION SEQUENCE
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Patent #:
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10/12/2010
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12250191
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10/13/2008
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Publication #:
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Pub Dt:
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02/12/2009
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Title:
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CMOS TRANSISTOR JUNCTION REGIONS FORMED BY A CVD ETCHING AND DEPOSITION SEQUENCE
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07/01/2014
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13225677
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09/06/2011
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03/07/2013
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Title:
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09/09/2014
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13282896
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10/27/2011
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05/02/2013
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03/17/2015
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13324053
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12/13/2011
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06/13/2013
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Title:
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08/04/2015
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13326586
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08/09/2012
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04/05/2016
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13327670
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12/15/2011
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12/20/2012
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Title:
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02/14/2017
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13335257
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12/22/2011
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Pub Dt:
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08/02/2012
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Title:
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11/25/2014
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13398641
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02/16/2012
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06/20/2013
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Title:
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Power budgeting between a processing core, a graphics core, and a bus on an integrated circuit when a limit is reached
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03/17/2015
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13631865
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09/29/2012
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04/03/2014
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Title:
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LOAD BALANCING AND MERGING OF TESSELLATION THREAD WORKLOADS
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09/11/2018
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13729579
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12/28/2012
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07/03/2014
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07/08/2014
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13780066
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02/28/2013
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07/11/2013
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Title:
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Dynamically Allocating A Power Budget Over Multiple Domains Of A Processor
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10/27/2015
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13782473
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03/01/2013
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07/11/2013
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06/14/2016
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13793037
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03/11/2013
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09/11/2014
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06/21/2016
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13991899
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06/05/2013
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10/03/2013
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Title:
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METHODS AND APPARATUSES TO FORM SELF-ALIGNED CAPS
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12/01/2015
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13992598
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06/07/2013
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Pub Dt:
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09/26/2013
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Title:
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CAPPING DIELECTRIC STRUCTURE FOR TRANSISTOR GATES
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02/06/2018
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13997412
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04/03/2014
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Pub Dt:
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02/05/2015
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Title:
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METHOD AND DEVICE FOR SECURE COMMUNICATIONS OVER A NETWORK USING A HARDWARE SECURITY ENGINE
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06/21/2016
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14142726
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12/27/2013
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Pub Dt:
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07/02/2015
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Title:
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Assisted Coherent Shared Memory
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07/14/2015
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14143939
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12/30/2013
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Pub Dt:
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04/24/2014
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Title:
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DYNAMICALLY ALLOCATING A POWER BUDGET OVER MULTIPLE DOMAINS OF A PROCESSOR
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Patent #:
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05/31/2016
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14451807
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08/05/2014
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11/20/2014
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07/11/2017
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14526040
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10/28/2014
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02/12/2015
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Title:
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METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING POWER AND PERFORMANCE BALANCING BETWEEN MULTIPLE PROCESSING ELEMENTS AND/OR A COMMUNICATION BUS
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02/21/2017
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14609620
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01/30/2015
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05/21/2015
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03/28/2017
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14625528
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02/18/2015
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06/11/2015
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04/18/2017
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14675613
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03/31/2015
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09/24/2015
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01/03/2017
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14855553
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09/16/2015
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01/07/2016
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11/08/2016
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14925741
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10/28/2015
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02/18/2016
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01/02/2018
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15116453
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08/03/2016
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01/12/2017
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07/31/2018
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15138505
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04/26/2016
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10/27/2016
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06/12/2018
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05/18/2016
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09/08/2016
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06/08/2016
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02/23/2017
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08/06/2019
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12/02/2016
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03/23/2017
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04/06/2017
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08/14/2018
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15431527
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02/13/2017
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06/01/2017
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10/15/2019
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15477506
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04/03/2017
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07/20/2017
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06/11/2019
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15611876
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12/21/2017
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12/04/2018
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05/24/2018
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07/28/2020
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15947829
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04/08/2018
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08/09/2018
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PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES
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07/07/2020
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15947830
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04/08/2018
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08/09/2018
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Title:
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PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES
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07/28/2020
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15947831
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04/08/2018
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08/09/2018
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PROCESSORS HAVING VIRTUALLY CLUSTERED CORES AND CACHE SLICES
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08/27/2019
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15966397
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04/30/2018
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11/01/2018
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08/11/2020
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08/14/2018
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03/07/2019
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01/21/2020
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11/26/2018
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04/11/2019
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07/07/2020
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01/16/2019
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07/11/2019
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08/31/2021
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05/24/2019
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11/21/2019
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11/16/2021
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07/31/2019
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11/21/2019
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07/28/2020
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09/03/2019
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12/26/2019
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NONE
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16908478
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06/22/2020
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10/08/2020
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NONE
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17402927
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08/16/2021
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12/02/2021
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Method, Apparatus, And System For Energy Efficiency And Energy Conservation Including Power And Performance Balancing Between Multiple Processing Elements And/Or A Communication Bus
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NONE
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11/22/2022
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17645202
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12/20/2021
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04/14/2022
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Title:
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CONTROLLING OPERATING VOLTAGE OF A PROCESSOR
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