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Patent Assignment Details
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Reel/Frame:023519/0599   Pages: 10
Recorded: 11/16/2009
Attorney Dkt #:121416*
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 15
1
Patent #:
Issue Dt:
04/02/2002
Application #:
09406941
Filing Dt:
09/28/1999
Title:
METHOD OF GENERATING FINITE STATE DATA FOR DESIGNING A CASCADE DECOMPOSED LOGIC CIRCUIT
2
Patent #:
Issue Dt:
08/30/2005
Application #:
09637532
Filing Dt:
08/11/2000
Title:
PARALLEL COUNTER AND A MULTIPLICATION LOGIC CIRCUIT
3
Patent #:
Issue Dt:
04/19/2005
Application #:
09769954
Filing Dt:
01/25/2001
Publication #:
Pub Dt:
02/28/2002
Title:
PARALLEL COUNTER AND A MULTIPLICATION LOGIC CIRCUIT
4
Patent #:
Issue Dt:
09/30/2003
Application #:
09771922
Filing Dt:
01/29/2001
Publication #:
Pub Dt:
11/22/2001
Title:
METHOD AND APPARATUS FOR BINARY ENCODING LOGIC CIRCUITS
5
Patent #:
Issue Dt:
11/21/2006
Application #:
09898752
Filing Dt:
07/03/2001
Publication #:
Pub Dt:
09/26/2002
Title:
MULTIPLICATION LOGIC CIRCUIT
6
Patent #:
Issue Dt:
11/14/2006
Application #:
09917257
Filing Dt:
07/27/2001
Publication #:
Pub Dt:
06/20/2002
Title:
PARALLEL COUNTER AND A LOGIC CIRCUIT FOR PERFORMING MULTIPLICATION
7
Patent #:
Issue Dt:
09/25/2007
Application #:
10472658
Filing Dt:
09/22/2003
Publication #:
Pub Dt:
05/27/2004
Title:
MULTIPLICATION LOGIC CIRCUIT
8
Patent #:
Issue Dt:
08/21/2007
Application #:
10714408
Filing Dt:
11/14/2003
Publication #:
Pub Dt:
08/05/2004
Title:
LOGIC CIRCUIT AND METHOD FOR CARRY AND SUM GENERATION AND METHOD OF DESIGNING SUCH A LOGIC CIRCUIT
9
Patent #:
Issue Dt:
01/30/2007
Application #:
10755723
Filing Dt:
01/12/2004
Publication #:
Pub Dt:
11/25/2004
Title:
SUM BIT GENERATION CIRCUIT
10
Patent #:
Issue Dt:
06/21/2005
Application #:
10757712
Filing Dt:
01/14/2004
Publication #:
Pub Dt:
10/14/2004
Title:
LOGIC CIRCUIT
11
Patent #:
Issue Dt:
12/11/2007
Application #:
10774363
Filing Dt:
02/06/2004
Publication #:
Pub Dt:
11/11/2004
Title:
METHOD AND DEVICE FOR PERFORMING OPERATIONS INVOLVING MULTIPLICATION OF SELECTIVELY PARTITIONED BINARY INPUTS USING BOOTH ENCODING
12
Patent #:
Issue Dt:
05/09/2006
Application #:
10776938
Filing Dt:
02/11/2004
Publication #:
Pub Dt:
11/11/2004
Title:
LOGIC CIRCUITS FOR PERFORMING THRESHOLD FUNCTIONS
13
Patent #:
Issue Dt:
10/26/2010
Application #:
10867179
Filing Dt:
06/14/2004
Publication #:
Pub Dt:
05/05/2005
Title:
CALCULATING APPARATUS AND METHOD FOR USE IN A MAXIMUM LIKELIHOOD DETECTOR AND/OR DECODER
14
Patent #:
Issue Dt:
08/28/2007
Application #:
10867216
Filing Dt:
06/14/2004
Publication #:
Pub Dt:
02/24/2005
Title:
MAXIMUM LIKELIHOOD DETECTOR AND/OR DECODER
15
Patent #:
Issue Dt:
05/31/2011
Application #:
11766540
Filing Dt:
06/21/2007
Publication #:
Pub Dt:
01/03/2008
Title:
LIKELIHOOD DETECTOR APPARATUS AND METHOD
Assignor
1
Exec Dt:
08/14/2009
Assignee
1
17 WESTMINISTER COURT, HIPLEY STREET
WOKING, SURREY, UNITED KINGDOM GU22 9LG
Correspondence name and address
SCHWABE WILLIAMSON & WYATT P.C.
1420 5TH AVENUE, SUITE 3010
SEATTLE, WA 98101

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