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Reel/Frame:055671/0612   Pages: 235
Recorded: 12/24/2020
Attorney Dkt #:509335/3097
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 3284
Page 3 of 33
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
1
Patent #:
Issue Dt:
04/01/2003
Application #:
09943804
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
01/17/2002
Title:
INTEGRATED IC CHIP PACKAGE FOR ELECTRONIC IMAGE SENSOR DIE
2
Patent #:
Issue Dt:
06/10/2003
Application #:
09944347
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
02/28/2002
Title:
METAL REDISTRIBUTION LAYER HAVING SOLDERABLE PADS AND WIRE BONDABLE PADS
3
Patent #:
Issue Dt:
09/26/2006
Application #:
09949288
Filing Dt:
09/07/2001
Publication #:
Pub Dt:
08/22/2002
Title:
SYSTEM AND METHOD FOR DATA TRANSMISSION
4
Patent #:
Issue Dt:
05/13/2003
Application #:
09951280
Filing Dt:
09/13/2001
Publication #:
Pub Dt:
03/13/2003
Title:
ELECTRONIC CIRCUIT AND METHOD FOR TESTING AND REFRESHING NON-VOLATILE MEMORY
5
Patent #:
Issue Dt:
04/08/2003
Application #:
09951336
Filing Dt:
09/10/2001
Title:
VOLTAGE-CONTROLLED OSCILLATOR FREQUENCY AUTO-CALIBRATING SYSTEM
6
Patent #:
Issue Dt:
03/04/2003
Application #:
09954387
Filing Dt:
09/10/2001
Publication #:
Pub Dt:
03/13/2003
Title:
INTEGRATED CIRCUIT FOR CONCURRENT FLASH MEMORY WITH UNEVEN ARRAY ARCHITECTURE
7
Patent #:
Issue Dt:
04/29/2003
Application #:
09955255
Filing Dt:
09/19/2001
Publication #:
Pub Dt:
03/20/2003
Title:
LOW NOISE METHOD AND APPARATUS FOR DRIVING ELECTROLUMINESCENT PANELS
8
Patent #:
Issue Dt:
11/27/2007
Application #:
09955278
Filing Dt:
09/11/2001
Title:
METHOD AND APPARATUS FOR IMPROVED HIGH-SPEED ADAPTIVE EQUALIZATION
9
Patent #:
Issue Dt:
04/08/2003
Application #:
09955563
Filing Dt:
09/17/2001
Title:
PROGRAMMABLE ANALOG TAPPED DELAY LINE FILTER HAVING CASCADED DIFFERENTIAL DELAY CELLS
10
Patent #:
Issue Dt:
07/11/2006
Application #:
09957061
Filing Dt:
09/20/2001
Publication #:
Pub Dt:
03/20/2003
Title:
SERIAL COMMUNICATION DEVICE WITH DYNAMIC FILTER ALLOCATION
11
Patent #:
Issue Dt:
03/21/2006
Application #:
09957097
Filing Dt:
09/19/2001
Title:
METHOD AND APPARATUS FOR A VIRTUAL MEMORY FILE SYSTEM
12
Patent #:
Issue Dt:
09/13/2005
Application #:
09957283
Filing Dt:
09/20/2001
Publication #:
Pub Dt:
08/05/2004
Title:
REGISTER BANK
13
Patent #:
Issue Dt:
06/28/2005
Application #:
09957289
Filing Dt:
09/20/2001
Publication #:
Pub Dt:
03/27/2003
Title:
SERIAL COMMUNICATION DEVICE WITH MULTI-MODE OPERATION OF MESSAGE RECEIVE BUFFERS
14
Patent #:
Issue Dt:
11/05/2002
Application #:
09960544
Filing Dt:
09/21/2001
Title:
REPROGRAMMABLE FUSE AND METHOD OF OPERATING
15
Patent #:
Issue Dt:
07/08/2003
Application #:
09960589
Filing Dt:
09/21/2001
Publication #:
Pub Dt:
03/27/2003
Title:
FOLDED CASCODE HIGH VOLTAGE OPERATIONAL AMPLIFIER WITH CLASS AB SOURCE FOLLOWER OUTPUT STAGE
16
Patent #:
Issue Dt:
11/25/2003
Application #:
09961517
Filing Dt:
09/24/2001
Publication #:
Pub Dt:
03/27/2003
Title:
LOW-POWER OUTPUT CONTROLLED CIRCUIT
17
Patent #:
Issue Dt:
06/07/2005
Application #:
09962980
Filing Dt:
09/21/2001
Title:
METHOD AND APPARATUS FOR EXTENDING STORAGE FUNCTIONALITY AT THE BIOS LEVEL
18
Patent #:
Issue Dt:
10/08/2002
Application #:
09964762
Filing Dt:
09/27/2001
Title:
OPERATIONAL AMPLIFIER THAT IS CONFIGURABLE AS A PROGRAMMABLE GAIN AMPLIFIER OF A GENERAL PURPOSE AMPLIFIER
19
Patent #:
Issue Dt:
10/10/2006
Application #:
09971748
Filing Dt:
10/04/2001
Publication #:
Pub Dt:
04/11/2002
Title:
PHASE-LOCKED LOOP CIRCUIT
20
Patent #:
Issue Dt:
07/15/2003
Application #:
09972179
Filing Dt:
10/05/2001
Publication #:
Pub Dt:
01/31/2002
Title:
SELF ALIGNED METHOD OF FORMING A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS, AND A MEMORY ARRAY MADE THEREBY
21
Patent #:
Issue Dt:
07/06/2004
Application #:
09972558
Filing Dt:
10/08/2001
Publication #:
Pub Dt:
09/25/2003
Title:
AUDIO SPECTRUM ANALYZER IMPLEMENTED WITH A MINIMUM NUMBER OF MULTIPLY OPERATIONS
22
Patent #:
Issue Dt:
03/30/2004
Application #:
09976511
Filing Dt:
10/11/2001
Publication #:
Pub Dt:
06/06/2002
Title:
MONOLITHIC LOSS-OF-SIGNAL DETECT CIRCUITRY
23
Patent #:
Issue Dt:
07/12/2005
Application #:
09982413
Filing Dt:
10/17/2001
Publication #:
Pub Dt:
04/17/2003
Title:
SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH BURIED BIT-LINE AND VERTICAL WORD LINE TRANSISTOR
24
Patent #:
Issue Dt:
02/20/2007
Application #:
09993308
Filing Dt:
11/23/2001
Publication #:
Pub Dt:
10/31/2002
Title:
APPARATUS AND METHOD FOR TRANSMITTING AN ANISOCHRONIC DATA STREAM ON AN ISOCHRONIC TRANSMISSION ROUTE
25
Patent #:
Issue Dt:
07/01/2003
Application #:
09994181
Filing Dt:
11/26/2001
Publication #:
Pub Dt:
05/29/2003
Title:
RING TOPOLOGY BASED VOLTAGE CONTROLLED OSCILLATOR
26
Patent #:
Issue Dt:
12/16/2003
Application #:
09999653
Filing Dt:
10/25/2001
Publication #:
Pub Dt:
05/01/2003
Title:
HUBLESS DOCKING STATION HAVING USB PORTS
27
Patent #:
Issue Dt:
08/19/2003
Application #:
09999709
Filing Dt:
10/30/2001
Publication #:
Pub Dt:
05/01/2003
Title:
ON-CHIP INDUCTOR USING ACTIVE MAGNETIC ENERGY RECOVERY
28
Patent #:
Issue Dt:
01/11/2005
Application #:
10001557
Filing Dt:
10/24/2001
Publication #:
Pub Dt:
05/30/2002
Title:
SELF-ALIGNED NON-VOLATILE MEMORY CELL
29
Patent #:
Issue Dt:
07/08/2003
Application #:
10002036
Filing Dt:
11/01/2001
Publication #:
Pub Dt:
05/08/2003
Title:
NON-VOLATILE FLASH FUSE ELEMENT
30
Patent #:
Issue Dt:
04/19/2005
Application #:
10004390
Filing Dt:
10/25/2001
Publication #:
Pub Dt:
05/01/2003
Title:
METHOD AND APPARATUS FOR CONFIGURATION CONTROL AND POWER MANAGEMENT THROUGH SPECIAL SIGNALING
31
Patent #:
Issue Dt:
07/22/2003
Application #:
10005317
Filing Dt:
11/06/2001
Publication #:
Pub Dt:
05/15/2003
Title:
DUAL MODE HIGH VOLTAGE POWER SUPPLY FOR PROVIDING INCREASED SPEED IN PROGRAMMING DURING TESTING OF LOW VOLTAGE NON-VOLATILE MEMORIES
32
Patent #:
Issue Dt:
09/30/2003
Application #:
10010693
Filing Dt:
12/05/2001
Publication #:
Pub Dt:
12/05/2002
Title:
A CURRENT MEASURING TERMINAL ASSEMBLY FOR A BATTERY
33
Patent #:
Issue Dt:
03/22/2005
Application #:
10013581
Filing Dt:
12/10/2001
Publication #:
Pub Dt:
05/09/2002
Title:
LOW VOLTAGE RAIL-TO-RAIL CMOS INPUT STAGE
34
Patent #:
Issue Dt:
05/05/2009
Application #:
10014664
Filing Dt:
12/14/2001
Publication #:
Pub Dt:
08/15/2002
Title:
METHOD OF AND APPARATUS FOR TRANSFERRING DATA
35
Patent #:
Issue Dt:
05/11/2004
Application #:
10017608
Filing Dt:
12/14/2001
Publication #:
Pub Dt:
06/19/2003
Title:
SYSTEM AND METHOD FOR PROVIDING ASYNCHRONOUS SRAM FUNCTIONALITY WITH A DRAM ARRAY
36
Patent #:
Issue Dt:
04/17/2007
Application #:
10022040
Filing Dt:
12/17/2001
Title:
ASYNCHRONOUS FAULT-TOLERANT ENCLOSURE SERVICES INTERFACE
37
Patent #:
Issue Dt:
01/21/2003
Application #:
10022314
Filing Dt:
12/18/2001
Publication #:
Pub Dt:
08/22/2002
Title:
ELECTRICALLY-ERASEABLE PROGRAMMABLE READ-ONLY MEMORY HAVING REDUCED-PAGE-SIZE PROGRAM AND ERASE
38
Patent #:
Issue Dt:
01/13/2004
Application #:
10024871
Filing Dt:
12/19/2001
Publication #:
Pub Dt:
04/24/2003
Title:
METHOD AND APPARATUS FOR END OF DISCHARGE INDICATION BASED ON CRITICAL ENERGY REQUIREMENT
39
Patent #:
Issue Dt:
10/28/2003
Application #:
10027665
Filing Dt:
12/20/2001
Publication #:
Pub Dt:
06/26/2003
Title:
METHOD AND SYSTEM FOR DYNAMICALLY CLOCKING DIGITAL SYSTEMS BASED ON POWER USAGE
40
Patent #:
Issue Dt:
05/17/2005
Application #:
10034067
Filing Dt:
12/28/2001
Title:
BURIED POWER BUSS UTILIZED AS A SINKER FOR HIGH CURRENT, HIGH POWER SEMICONDUCTOR DEVICES AND A METHOD FOR PROVIDING THE SAME
41
Patent #:
Issue Dt:
09/09/2003
Application #:
10039916
Filing Dt:
10/29/2001
Publication #:
Pub Dt:
05/01/2003
Title:
HIGH VOLTAGE BIT/COLUMN LATCH FOR VCC OPERATION
42
Patent #:
Issue Dt:
05/11/2004
Application #:
10040540
Filing Dt:
12/28/2001
Title:
VOLTAGE LEVEL-SHIFTING CONTROL CIRCUIT FOR ELECTRONIC SWITCH
43
Patent #:
Issue Dt:
05/20/2003
Application #:
10040724
Filing Dt:
10/31/2001
Publication #:
Pub Dt:
05/01/2003
Title:
SENICONDUCTOR ARRAY OF FLOATING GATE MEMORY CELLS AND STRAP REGIONS
44
Patent #:
Issue Dt:
03/15/2005
Application #:
10044273
Filing Dt:
01/10/2002
Publication #:
Pub Dt:
07/10/2003
Title:
HIGH VOLTAGE GENERATION AND REGULATION SYSTEM FOR DIGITAL MULTILEVEL NONVOLATILE MEMORY
45
Patent #:
Issue Dt:
11/02/2004
Application #:
10044821
Filing Dt:
01/10/2002
Publication #:
Pub Dt:
07/10/2003
Title:
BIAS DISTRIBUTION NETWORK FOR DIGITAL MULTILEVEL NONVOLATILE FLASH MEMORY
46
Patent #:
Issue Dt:
03/02/2004
Application #:
10051907
Filing Dt:
01/16/2002
Title:
RAID 1 WRITE MIRRORING METHOD FOR HOST ADAPTERS
47
Patent #:
Issue Dt:
04/27/2004
Application #:
10051960
Filing Dt:
01/16/2002
Title:
RAID 1 READ MIRRORING METHOD FOR HOST ADAPTERS
48
Patent #:
Issue Dt:
04/15/2003
Application #:
10052278
Filing Dt:
01/17/2002
Title:
HIGH SPEED BIAS VOLTAGE GENERATING CIRCUIT
49
Patent #:
Issue Dt:
09/16/2003
Application #:
10056412
Filing Dt:
01/22/2002
Title:
EXTENDED FREQUENCY RANGE VOLTAGE-CONTROLLED OSCILLATOR
50
Patent #:
Issue Dt:
11/19/2002
Application #:
10071612
Filing Dt:
02/08/2002
Publication #:
Pub Dt:
08/15/2002
Title:
SLAVED SUPPLY FOR SERIAL LINK, OF MASTER SLAVE TYPE
51
Patent #:
Issue Dt:
01/21/2003
Application #:
10073036
Filing Dt:
02/12/2002
Title:
VARIABLE READ/WRITE MARGIN HIGH-PERFORMANCE SOFT-ERROR TOLERANT SRAM BIT CELL
52
Patent #:
Issue Dt:
03/15/2005
Application #:
10076105
Filing Dt:
02/14/2002
Publication #:
Pub Dt:
08/14/2003
Title:
A SWITCHABLE HOT-DOCKING INTERFACE FOR A PORTABLE COMPUTER FOR HOT-DOCKING THE PORTABLE COMPUTER TO A DOCKING STATION
53
Patent #:
Issue Dt:
02/28/2006
Application #:
10077466
Filing Dt:
02/14/2002
Title:
METHOD FOR PROVIDING A CONFIGURATION EXTENSIBLE MARKUP LANGUAGE (XML) PAGE TO A USER FOR CONFIGURING AN XML BASED STORAGE HANDLING CONTOLLER
54
Patent #:
Issue Dt:
02/03/2009
Application #:
10081152
Filing Dt:
02/25/2002
Publication #:
Pub Dt:
11/14/2002
Title:
METHOD AND APPARATUS FOR SCHEDULING DATA ON A MEDIUM
55
Patent #:
Issue Dt:
06/22/2004
Application #:
10081821
Filing Dt:
02/20/2002
Publication #:
Pub Dt:
07/11/2002
Title:
INTEGRATED CIRCUIT AND METHOD OF CONTROLLING OUTPUT IMPEDANCE
56
Patent #:
Issue Dt:
01/25/2005
Application #:
10086937
Filing Dt:
02/28/2002
Publication #:
Pub Dt:
08/28/2003
Title:
ULTRA-HIGH LINEARITY RF PASSIVE MIXER
57
Patent #:
Issue Dt:
01/27/2004
Application #:
10096739
Filing Dt:
03/12/2002
Publication #:
Pub Dt:
07/18/2002
Title:
METHOD OF CONTROLLING THE TURN OFF CHARACTERISTICS OF A VCSEL DIODE
58
Patent #:
Issue Dt:
11/05/2002
Application #:
10100535
Filing Dt:
03/18/2002
Publication #:
Pub Dt:
08/08/2002
Title:
HIGH-SPEED, LOW-POWER SAMPLE AND HOLD CIRCUIT
59
Patent #:
Issue Dt:
10/04/2005
Application #:
10105741
Filing Dt:
03/20/2002
Publication #:
Pub Dt:
09/25/2003
Title:
A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH BURIED BIT-LINE AND RAISED SOURCE LINE
60
Patent #:
Issue Dt:
08/01/2006
Application #:
10108063
Filing Dt:
03/26/2002
Title:
METHOD AND APPARATUS FOR COMBINATION HOST BUS ADAPTER
61
Patent #:
Issue Dt:
03/06/2007
Application #:
10113797
Filing Dt:
03/29/2002
Title:
GENERIC PACKET PARSER
62
Patent #:
Issue Dt:
11/29/2005
Application #:
10115734
Filing Dt:
04/02/2002
Title:
METHOD AND APPARATUS FOR MINIMIZING OPTION ROM BIOS CODE
63
Patent #:
Issue Dt:
07/11/2006
Application #:
10119983
Filing Dt:
04/10/2002
Publication #:
Pub Dt:
10/16/2003
Title:
METHOD AND APPARATUS FOR CONTROLLING A FAN
64
Patent #:
Issue Dt:
08/19/2003
Application #:
10121377
Filing Dt:
04/11/2002
Title:
SINGLE-ENDED CURRENT SENSE AMPLIFIER
65
Patent #:
Issue Dt:
12/01/2009
Application #:
10125697
Filing Dt:
04/18/2002
Publication #:
Pub Dt:
10/23/2003
Title:
BOOTABLE SOLID STATE FLOPPY DISK DRIVE
66
Patent #:
Issue Dt:
10/16/2007
Application #:
10126466
Filing Dt:
04/19/2002
Title:
DATA STREAM PERMUTATION APPLICABLE TO LARGE DIMENSIONS
67
Patent #:
Issue Dt:
01/13/2004
Application #:
10131064
Filing Dt:
04/24/2002
Publication #:
Pub Dt:
11/07/2002
Title:
METHOD AND APPARATUS FOR HIGH-VOLTAGE BATTERY ARRAY MONITORING SENSORS NETWORK
68
Patent #:
Issue Dt:
08/08/2006
Application #:
10131387
Filing Dt:
04/23/2002
Title:
METHOD AND APPARATUS FOR DUAL PORTING A SINGLE PORT SERIAL ATA DISK DRIVE
69
Patent #:
Issue Dt:
05/22/2007
Application #:
10132788
Filing Dt:
04/24/2002
Publication #:
Pub Dt:
10/30/2003
Title:
HIGH THROUGHPUT AES ARCHITECTURE
70
Patent #:
Issue Dt:
06/17/2003
Application #:
10135916
Filing Dt:
04/29/2002
Title:
METHOD OF ERASING NONVOLATILE TUNNELING INJECTOR MEMORY CELL
71
Patent #:
Issue Dt:
04/01/2003
Application #:
10136797
Filing Dt:
04/30/2002
Title:
METHOD OF FORMING A SEMICONDUCTOR ARRAY OF FLOATING GATE MEMORY CELLS HAVING STRAP REGIONS AND A PERIPHERAL LOGIC DEVICE REGION
72
Patent #:
Issue Dt:
05/30/2006
Application #:
10137690
Filing Dt:
05/02/2002
Publication #:
Pub Dt:
11/06/2003
Title:
MULTIPLE DRIVE CONTROLLER
73
Patent #:
Issue Dt:
01/16/2007
Application #:
10138496
Filing Dt:
05/06/2002
Publication #:
Pub Dt:
02/20/2003
Title:
DATA SWITCHING SYSTEM
74
Patent #:
Issue Dt:
12/23/2003
Application #:
10141051
Filing Dt:
05/07/2002
Publication #:
Pub Dt:
11/13/2003
Title:
METHOD AND APPARATUS FOR EFFICIENTLY DRIVING A LOW-VOLTAGE DEVICE FROM A WIDE-RANGE INPUT SUPPLY
75
Patent #:
Issue Dt:
09/23/2003
Application #:
10143225
Filing Dt:
05/09/2002
Title:
ULTRA SMALL THIN WINDOWS IN FLOATING GATE TRANSISTORS DEFINED BY LOST NITRIDE SPACERS
76
Patent #:
Issue Dt:
10/04/2005
Application #:
10145160
Filing Dt:
05/13/2002
Publication #:
Pub Dt:
11/21/2002
Title:
Tuned antenna resonant circuit of a passive transponder
77
Patent #:
Issue Dt:
03/16/2004
Application #:
10146569
Filing Dt:
05/14/2002
Publication #:
Pub Dt:
11/20/2003
Title:
SELF ALIGNED METHOD OF FORMING A SEMICONDUCTOR ARRAY OF NON-VOLATILE MEMORY CELLS
78
Patent #:
Issue Dt:
10/02/2007
Application #:
10147699
Filing Dt:
05/16/2002
Publication #:
Pub Dt:
11/20/2003
Title:
RF PASSIVE MIXER WITH DC OFFSET TRACKING AND LOCAL OSCILLATOR DC BIAS LEVEL-SHIFTING NETWORK FOR REDUCING EVEN-ORDER DISTORTION
79
Patent #:
Issue Dt:
10/28/2003
Application #:
10147959
Filing Dt:
05/15/2002
Title:
METHOD AND APPARATUS FOR PROGRAMMING NON-VOLATILE MEMORY CELLS
80
Patent #:
Issue Dt:
11/29/2005
Application #:
10153549
Filing Dt:
05/21/2002
Title:
SOFTWARE BASED SYSTEM AND METHOD FOR I/O CHIP HIDING OF PROCESSOR BASED CONTROLLERS FROM OPERATING SYSTEM
81
Patent #:
Issue Dt:
07/26/2005
Application #:
10157097
Filing Dt:
05/29/2002
Publication #:
Pub Dt:
12/04/2003
Title:
COMMUNICATION SYSTEM AND METHODOLOGY FOR ADDRESSING AND SENDING DATA OF DISSIMILAR TYPE AND SIZE ACROSS CHANNELS FORMED WITHIN A LOCALLY SYNCHRONIZED BUS
82
Patent #:
Issue Dt:
03/29/2005
Application #:
10157673
Filing Dt:
05/29/2002
Publication #:
Pub Dt:
12/04/2003
Title:
COMMUNICATION SYSTEM AND METHODOLOGY FOR SENDING A DESIGNATOR FOR AT LEAST ONE OF A SET OF TIME-DIVISION MULTIPLEXED CHANNELS FORWARDED ACROSS A LOCALLY SYNCHRONIZED BUS
83
Patent #:
Issue Dt:
05/06/2003
Application #:
10159648
Filing Dt:
05/29/2002
Title:
DUAL-MIXER LOSS OF SIGNAL DETECTION CIRCUIT
84
Patent #:
Issue Dt:
08/24/2004
Application #:
10167959
Filing Dt:
06/11/2002
Publication #:
Pub Dt:
01/02/2003
Title:
PROCESS FOR MANUFACTURING A DMOS TRANSISTOR
85
Patent #:
Issue Dt:
04/12/2005
Application #:
10167961
Filing Dt:
06/11/2002
Publication #:
Pub Dt:
01/02/2003
Title:
PROCESS FOR MANUFACTURING A DMOS TRANSISTOR
86
Patent #:
Issue Dt:
08/23/2005
Application #:
10170098
Filing Dt:
06/11/2002
Publication #:
Pub Dt:
01/02/2003
Title:
PROCESS FOR DOPING A SEMICONDUCTOR BODY
87
Patent #:
Issue Dt:
09/28/2004
Application #:
10176220
Filing Dt:
06/19/2002
Title:
METHOD AND SYSTEM FOR PROVIDING A POWER LATERAL PNP TRANSISTOR USING A BURIED POWER BUSS
88
Patent #:
Issue Dt:
05/20/2003
Application #:
10176285
Filing Dt:
06/19/2002
Title:
METHOD AND SYSTEM FOR PROVIDING A POWER LATERAL PNP TRANSISTOR USING A BURIED POWER BUSS
89
Patent #:
Issue Dt:
02/05/2008
Application #:
10180696
Filing Dt:
06/26/2002
Publication #:
Pub Dt:
01/01/2004
Title:
COMMUNICATION SYSTEM AND METHOD FOR SENDING ISOCHRONOUS STREAMING DATA WITHIN A FRAME SEGMENT USING A SIGNALING BYTE
90
Patent #:
Issue Dt:
10/16/2007
Application #:
10180729
Filing Dt:
06/26/2002
Publication #:
Pub Dt:
01/01/2004
Title:
COMMUNICATION SYSTEM AND METHOD FOR SENDING ASYNCHRONOUS DATA AND/OR ISOCHRONOUS STREAMING DATA ACROSS A SYNCHRONOUS NETWORK WITHIN A FRAME SEGMENT USING A CODING VIOLATION TO SIGNIFY AT LEAST THE BEGINNING OF A DATA TRANSFER
91
Patent #:
Issue Dt:
01/16/2007
Application #:
10180741
Filing Dt:
06/26/2002
Publication #:
Pub Dt:
01/01/2004
Title:
COMMUNICATION SYSTEM AND METHOD FOR SENDING ISOCHRONOUS STREAMING DATA ACROSS A SYNCHRONOUS NETWORK WITHIN A FRAME SEGMENT USING A CODING VIOLATION TO SIGNIFY INVALID OR EMPTY BYTES WITHIN THE FRAME SEGMENT
92
Patent #:
Issue Dt:
06/29/2004
Application #:
10183834
Filing Dt:
06/25/2002
Publication #:
Pub Dt:
07/03/2003
Title:
SELF ALIGNED METHOD OF FORMING A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH HORIZONTALLY ORIENTED EDGES, AND A MEMORY ARRAY THEREBY
93
Patent #:
Issue Dt:
10/24/2006
Application #:
10190348
Filing Dt:
07/05/2002
Title:
APPARATUS AND METHOD FOR EFFICIENT DATA TRANSPORT USING TRANSPARENT FRAMING PROCEDURE
94
Patent #:
Issue Dt:
03/01/2005
Application #:
10192291
Filing Dt:
07/09/2002
Publication #:
Pub Dt:
07/24/2003
Title:
An array of floating gate memory cells having strap regions and a peripheral logic device region
95
Patent #:
Issue Dt:
04/03/2007
Application #:
10193131
Filing Dt:
07/12/2002
Title:
HIGH SPEED I-O LOOPBACK TESTING WITH LOW SPEED DC TEST CAPABILITY
96
Patent #:
Issue Dt:
12/30/2003
Application #:
10197281
Filing Dt:
07/16/2002
Title:
HIGH D.C. VOLTAGE TO LOW D.C. VOLTAGE CIRCUIT CONVERTER
97
Patent #:
Issue Dt:
07/22/2003
Application #:
10201093
Filing Dt:
07/22/2002
Title:
METHOD OF PREVENTING SHIFT OF ALIGNMENT MARKS DURING RAPID THERMAL PROCESSING
98
Patent #:
Issue Dt:
04/19/2005
Application #:
10202077
Filing Dt:
07/23/2002
Publication #:
Pub Dt:
02/06/2003
Title:
PROCESS FOR THE TRANSFER OF DATA
99
Patent #:
Issue Dt:
06/01/2004
Application #:
10205289
Filing Dt:
07/24/2002
Publication #:
Pub Dt:
03/20/2003
Title:
METHOD OF FORMING A SEMICONDUCTOR ARRAY OF FLOATING GATE MEMORY CELLS AND STRAP REGIONS, AND A MEMORY ARRAY AND STRAP REGIONS MADE THEREBY
100
Patent #:
Issue Dt:
01/02/2007
Application #:
10209502
Filing Dt:
07/31/2002
Publication #:
Pub Dt:
02/05/2004
Title:
SINGLE DIE STITCH BONDING
Assignors
1
Exec Dt:
12/17/2020
2
Exec Dt:
12/17/2020
3
Exec Dt:
12/17/2020
4
Exec Dt:
12/17/2020
5
Exec Dt:
12/17/2020
Assignee
1
600 SOUTH FOURTH STREET
CTSO MAIL OPERATIONS, 7TH FLOOR
MINNEAPOLIS, MINNESOTA 55415
Correspondence name and address
ALYSHA SEKHON
425 LEXINGTON AVENUE
NEW YORK, NY 10017

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