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Reel/Frame:026138/0613   Pages: 10
Recorded: 04/15/2011
Attorney Dkt #:60961-28001.00
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 122
Page 2 of 2
Pages: 1 2
1
Patent #:
7889589
Issue Dt:
02/15/2011
Application #:
12053913
Filing Dt:
03/24/2008
Publication #:
US20090237972
Pub Dt:
09/24/2009
Title:
MEMORY INCLUDING PERIPHERY CIRCUITRY TO SUPPORT A PORTION OR ALL OF THE MULTIPLE BANKS OF MEMORY CELLS
2
Patent #:
NONE
Issue Dt:
Application #:
12071721
Filing Dt:
02/26/2008
Publication #:
US20090215206
Pub Dt:
08/27/2009
Title:
System and method for controlling a semiconductor manufacturing process
3
Patent #:
7728638
Issue Dt:
06/01/2010
Application #:
12109609
Filing Dt:
04/25/2008
Publication #:
US20090267663
Pub Dt:
10/29/2009
Title:
ELECTRONIC SYSTEM THAT ADJUSTS DLL LOCK STATE ACQUISITION TIME
4
Patent #:
7773438
Issue Dt:
08/10/2010
Application #:
12134485
Filing Dt:
06/06/2008
Publication #:
US20090303813
Pub Dt:
12/10/2009
Title:
INTEGRATED CIRCUIT THAT STORES FIRST AND SECOND DEFECTIVE MEMORY CELL ADDRESSES
5
Patent #:
7940582
Issue Dt:
05/10/2011
Application #:
12134540
Filing Dt:
06/06/2008
Publication #:
US20090303814
Pub Dt:
12/10/2009
Title:
INTEGRATED CIRCUIT THAT STORES DEFECTIVE MEMORY CELL ADDRESSES
6
Patent #:
7715264
Issue Dt:
05/11/2010
Application #:
12145146
Filing Dt:
06/24/2008
Publication #:
US20090316511
Pub Dt:
12/24/2009
Title:
METHOD AND APPARATUS FOR SELECTIVELY DISABLING TERMINATION CIRCUITRY
7
Patent #:
7894283
Issue Dt:
02/22/2011
Application #:
12188558
Filing Dt:
08/08/2008
Publication #:
US20100034038
Pub Dt:
02/11/2010
Title:
INTEGRATED CIRCUIT INCLUDING SELECTABLE ADDRESS AND DATA MULTIPLEXING MODE
8
Patent #:
7899961
Issue Dt:
03/01/2011
Application #:
12202485
Filing Dt:
09/02/2008
Publication #:
US20100057971
Pub Dt:
03/04/2010
Title:
MULTI-MODE BUS INVERSION METHOD AND APPARATUS
9
Patent #:
NONE
Issue Dt:
Application #:
12209542
Filing Dt:
09/12/2008
Publication #:
US20100070676
Pub Dt:
03/18/2010
Title:
Memory Data Bus Placement and Control
10
Patent #:
7872936
Issue Dt:
01/18/2011
Application #:
12212400
Filing Dt:
09/17/2008
Publication #:
US20100070696
Pub Dt:
03/18/2010
Title:
SYSTEM AND METHOD FOR PACKAGED MEMORY
11
Patent #:
NONE
Issue Dt:
Application #:
12239575
Filing Dt:
09/26/2008
Publication #:
US20100079150
Pub Dt:
04/01/2010
Title:
APPARATUS FOR THE DYNAMIC DETECTION, SELECTION AND DESELECTION OF LEAKING DECOUPLING CAPACITORS
12
Patent #:
7855929
Issue Dt:
12/21/2010
Application #:
12239624
Filing Dt:
09/26/2008
Publication #:
US20100080043
Pub Dt:
04/01/2010
Title:
APPARATUS FOR THE DYNAMIC DETECTION, SELECTION AND DESELECTION OF LEAKING DECOUPLING CAPACITORS
13
Patent #:
7755967
Issue Dt:
07/13/2010
Application #:
12240331
Filing Dt:
09/29/2008
Publication #:
US20100080075
Pub Dt:
04/01/2010
Title:
MEMORY DEVICE REFRESH METHOD AND APPARATUS
14
Patent #:
7872931
Issue Dt:
01/18/2011
Application #:
12251010
Filing Dt:
10/14/2008
Publication #:
US20100091595
Pub Dt:
04/15/2010
Title:
INTEGRATED CIRCUIT WITH CONTROL CIRCUIT FOR PERFORMING RETENTION TEST
15
Patent #:
7894290
Issue Dt:
02/22/2011
Application #:
12255755
Filing Dt:
10/22/2008
Publication #:
US20100097874
Pub Dt:
04/22/2010
Title:
METHOD AND APPARATUS FOR PERFORMING INTERNAL HIDDEN REFRESHES WHILE LATCHING READ/WRITE COMMANDS, ADDRESS AND DATA INFORMATION FOR LATER OPERATION
16
Patent #:
8797811
Issue Dt:
08/05/2014
Application #:
12273348
Filing Dt:
11/18/2008
Publication #:
US20100124130
Pub Dt:
05/20/2010
Title:
METHOD AND APPARATUS TO REDUCE POWER CONSUMPTION BY TRANSFERRING FUNCTIONALITY FROM MEMORY COMPONENTS TO A MEMORY INTERFACE
17
Patent #:
7965120
Issue Dt:
06/21/2011
Application #:
12275372
Filing Dt:
11/21/2008
Publication #:
US20100127746
Pub Dt:
05/27/2010
Title:
DIGITALLY CONTROLLED CML BUFFER
18
Patent #:
8189374
Issue Dt:
05/29/2012
Application #:
12826201
Filing Dt:
06/29/2010
Publication #:
US20100265763
Pub Dt:
10/21/2010
Title:
MEMORY DEVICE INCLUDING AN ELECTRODE HAVING AN OUTER PORTION WITH GREATER RESISTIVITY
19
Patent #:
8384062
Issue Dt:
02/26/2013
Application #:
12853791
Filing Dt:
08/10/2010
Publication #:
US20100321990
Pub Dt:
12/23/2010
Title:
Memory Including Vertical Bipolar Select Device and Resistive Memory Element
20
Patent #:
8039299
Issue Dt:
10/18/2011
Application #:
12856007
Filing Dt:
08/13/2010
Publication #:
US20100323493
Pub Dt:
12/23/2010
Title:
METHOD FOR FABRICATING AN INTEGRATED CIRCUIT INCLUDING RESISTIVITY CHANGING MATERIAL HAVING A PLANARIZED SURFACE
21
Patent #:
8468401
Issue Dt:
06/18/2013
Application #:
12856225
Filing Dt:
08/13/2010
Publication #:
US20100306605
Pub Dt:
12/02/2010
Title:
APPARATUS AND METHOD FOR MANUFACTURING A MULTIPLE-CHIP MEMORY DEVICE WITH MULTI-STAGE TESTING
22
Patent #:
7977987
Issue Dt:
07/12/2011
Application #:
12886791
Filing Dt:
09/21/2010
Publication #:
US20110006821
Pub Dt:
01/13/2011
Title:
SYSTEM AND METHOD FOR SIGNAL ADJUSTMENT
Assignor
1
QIMONDA NORTH AMERICA CORP
Exec Dt:
02/21/2011
Assignee
1
QIMONDA AG
GUSTAV-HEINEMANN-RING 212
MUNICH, GERMANY 81379
Correspondence name and address
BARRY E. BRETSCHNEIDER
C/O MORRISON & FOERSTER LLP
1650 TYSONS BLVD STE 400
MCLEAN, VA 22102

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