Total properties:
594
Page
4
of
6
Pages:
1 2 3 4 5 6
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10722636
|
Filing Dt:
|
11/25/2003
|
|
Title:
|
DELAY LOCKED LOOP FOR AN FPGA ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
|
Application #:
|
10724530
|
Filing Dt:
|
11/26/2003
|
|
Title:
|
CHIP CARRIER SUBSTRATE WITH A LAND GRID ARRAY AND EXTERNAL BOND TERMINALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2005
|
Application #:
|
10724531
|
Filing Dt:
|
11/26/2003
|
|
Title:
|
RADIATION SHIELDING DIE CARRIER PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
|
Application #:
|
10744160
|
Filing Dt:
|
12/22/2003
|
|
Title:
|
COMPOUND SEMICONDUTOR PROTECTION DEVICE FOR LOW VOLTAGE AND HIGH SPEED DATA LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
10752222
|
Filing Dt:
|
01/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/01/2005
| | | | |
|
Title:
|
RADIATION TOLERANT SRAM BIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10757028
|
Filing Dt:
|
01/13/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
|
Title:
|
DESIGN AND FABRICATION OF RUGGED FRED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
10758952
|
Filing Dt:
|
01/16/2004
|
|
Title:
|
Battery charging and discharging by using a bi-directional transistor
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2009
|
Application #:
|
10760126
|
Filing Dt:
|
01/16/2004
|
|
Title:
|
LINEARLY REGULATED BATTERY CHARGER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10760626
|
Filing Dt:
|
01/20/2004
|
|
Title:
|
METHOD AND APPARATUS TO SWITCH OPERATING MODES IN A PFM CONVERTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10761801
|
Filing Dt:
|
01/20/2004
|
|
Title:
|
DUAL-MODE PFM BOOST CONVERTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
10784903
|
Filing Dt:
|
02/20/2004
|
|
Title:
|
REPROGRAMMABLE METAL-TO-METAL ANTIFUSE EMPLOYING CARBON-CONTAINING ANTIFUSE MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10788536
|
Filing Dt:
|
02/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/01/2005
| | | | |
|
Title:
|
PIN OR NIP LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSORS AND STEERING DIODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
10802577
|
Filing Dt:
|
03/16/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/07/2004
| | | | |
|
Title:
|
SRAM BUS ARCHITECTURE AND INTERCONNECT TO AN FPGA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10811422
|
Filing Dt:
|
03/25/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR UNIVERSAL PROGRAM CONTROLLED BUS ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10821533
|
Filing Dt:
|
04/08/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
|
Title:
|
FIELD PROGRAMMABLE GATE ARRAY AND MICROCONTROLLER SYSTEM-ON-A-CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10829527
|
Filing Dt:
|
04/21/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/07/2004
| | | | |
|
Title:
|
ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10829596
|
Filing Dt:
|
04/21/2004
|
|
Title:
|
METHOD AND APPARATUS OF MEMORY CLEARING WITH MONITORING RAM MEMORY CELLS IN A FIELD PROGRAMMABLE GATED ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10843701
|
Filing Dt:
|
05/10/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/27/2005
| | | | |
|
Title:
|
PROGRAMMABLE SYSTEM ON A CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2009
|
Application #:
|
10845746
|
Filing Dt:
|
05/13/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/21/2004
| | | | |
|
Title:
|
SPRAY COATING APPARATUS AND FIXTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10850054
|
Filing Dt:
|
05/19/2004
|
|
Title:
|
PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
10850568
|
Filing Dt:
|
05/19/2004
|
|
Title:
|
PROGRAMMABLE SYSTEM ON A CHIP FOR TEMPERATURE MONITORING AND CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
10857472
|
Filing Dt:
|
05/28/2004
|
|
Title:
|
INTEGRATED CIRCUIT DEVICE HAVING STATE-SAVING AND INITIALIZATION FEATURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
10877043
|
Filing Dt:
|
06/25/2004
|
|
Title:
|
SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT INCLUDING DUAL-FUNCTION ANALOG AND DIGITAL INPUTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10877045
|
Filing Dt:
|
06/25/2004
|
|
Title:
|
INTEGRATED CIRCUIT INCLUDING PROGRAMMABLE LOGIC AND EXTERNAL-DEVICE CHIP-ENABLE OVERRIDE CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
|
Application #:
|
10877872
|
Filing Dt:
|
06/24/2004
|
|
Title:
|
THREE INPUT FIELD PROGRAMMABLE GATE ARRAY LOGIC CIRCUIT CONFIGURABLE AS A THREE INPUT LOOK UP TABLE, A D-LATCH OR A D FLIP-FLOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10877897
|
Filing Dt:
|
06/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/25/2004
| | | | |
|
Title:
|
CYCLIC REDUNDANCY CHECKING OF A FIELD PROGRAMMABLE GATE ARRAY HAVING AN SRAM MEMORY ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10898149
|
Filing Dt:
|
07/22/2004
|
|
Title:
|
NON-VOLATILE MEMORY ARCHITECTURE FOR PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10903473
|
Filing Dt:
|
07/29/2004
|
|
Title:
|
CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
10903636
|
Filing Dt:
|
07/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/24/2005
| | | | |
|
Title:
|
SPLIT PHASE INVERTERS FOR CCFL BACKLIGHT SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
10916214
|
Filing Dt:
|
08/10/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
ENHANCED FIELD PROGRAMMABLE GATE ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2006
|
Application #:
|
10916926
|
Filing Dt:
|
08/11/2004
|
|
Title:
|
CLOCK TREE NETWORK IN A FIELD PROGRAMMABLE GATE ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10933668
|
Filing Dt:
|
09/03/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/09/2006
| | | | |
|
Title:
|
PROTECTING A COLD CATHODE FLUORESCENT LAMP FROM A LARGE TRANSIENT CURRENT WHEN VOLTAGE SUPPLY TRANSITIONS FROM A LOW TO A HIGH VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10937889
|
Filing Dt:
|
09/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
|
Title:
|
OPTICAL AND TEMPERATURE FEEDBACKS TO CONTROL DISPLAY BRIGHTNESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
10941628
|
Filing Dt:
|
09/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR BUILDING TAMPER RESISTANT COATINGS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10948010
|
Filing Dt:
|
09/22/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
|
Title:
|
SYNCHRONOUS FIRST-IN/FIRST-OUT BLOCK MEMORY FOR A FIELD PROGRAMMABLE GATE ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10948048
|
Filing Dt:
|
09/22/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
APPARATUS AND METHOD OF ERROR DETECTION AND CORRECTION IN A RADIATION-HARDENED STATIC RANDOM ACCESS MEMORY FIELD- PROGRAMMABLE GATE ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
10955929
|
Filing Dt:
|
09/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/06/2006
| | | | |
|
Title:
|
FACE-TO-FACE BONDED I/O CIRCUIT DIE AND FUNCTIONAL LOGIC CIRCUIT DIE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2007
|
Application #:
|
10958668
|
Filing Dt:
|
10/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
CURRENT SHARING SCHEME FOR MULTIPLE CCF LAMP OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10959404
|
Filing Dt:
|
10/05/2004
|
|
Title:
|
SRAM CELL CONTROLLED BY NON-VOLATILE MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2007
|
Application #:
|
10959667
|
Filing Dt:
|
10/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
BALANCING TRANSFORMERS FOR RING BALANCER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
10970243
|
Filing Dt:
|
10/20/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR A TRANSFORMER CONFIGURATION WITH A TREE TOPOLOGY FOR CURRENT BALANCING IN GAS DISCHARGE LAMPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10970244
|
Filing Dt:
|
10/20/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR A TRANSFORMER CONFIGURATION FOR DRIVING MULTIPLE GAS DISCHARGE TUBES IN PARALLEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
10970248
|
Filing Dt:
|
10/20/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR FAULT PROTECTION IN A BALANCING TRANSFORMER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2009
|
Application #:
|
10997057
|
Filing Dt:
|
11/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/24/2005
| | | | |
|
Title:
|
METHOD OF FABRICATING SELF-ALIGNED SILICON CARBIDE SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
10997688
|
Filing Dt:
|
11/24/2004
|
|
Title:
|
CIRCUIT AND METHOD FOR SUPPLYING PROGRAMMING POTENTIAL AT VOLTAGES LARGER THAN BVDSS OF PROGRAMMING TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
11011752
|
Filing Dt:
|
12/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/21/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS TO DRIVE LED ARRAYS USING TIME SHARING TECHNIQUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
11011753
|
Filing Dt:
|
12/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/21/2005
| | | | |
|
Title:
|
LAMP CURRENT CONTROL USING PROFILE SYNTHESIZER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
11011754
|
Filing Dt:
|
12/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/21/2005
| | | | |
|
Title:
|
INVERTER WITH TWO SWITCHING STAGES FOR DRIVING LAMP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
11011760
|
Filing Dt:
|
12/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
|
Title:
|
CURRENT-MODE DIRECT-DRIVE INVERTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2006
|
Application #:
|
11016699
|
Filing Dt:
|
12/17/2004
|
|
Title:
|
INTEGRATED MULTI-FUNCTION ANALOG CIRCUIT INCLUDING VOLTAGE, CURRENT, AND TEMPERATURE MONITOR AND GATE-DRIVER CIRCUIT BLOCKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
11021092
|
Filing Dt:
|
12/22/2004
|
|
Title:
|
POWER-UP AND POWER-DOWN CIRCUIT FOR SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
11021472
|
Filing Dt:
|
12/23/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
|
Title:
|
NON-VOLATILE MEMORY CONFIGURATION SCHEME FOR VOLATILE-MEMORY-BASED PROGRAMMABLE CIRCUITS IN AN FPGA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
11022331
|
Filing Dt:
|
12/21/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/22/2006
| | | | |
|
Title:
|
VOLTAGE- AND TEMPERATURE-COMPENSATED RC OSCILLATOR CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2008
|
Application #:
|
11023295
|
Filing Dt:
|
12/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/01/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS TO CONTROL DISPLAY BRIGHTNESS WITH AMBIENT LIGHT CORRECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
11026336
|
Filing Dt:
|
12/29/2004
|
|
Title:
|
NON-VOLATILE LOOK-UP TABLE FOR AN FPGA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
11027788
|
Filing Dt:
|
12/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
|
Title:
|
ESD PROTECTION STRUCTURE FOR I/O PAD SUBJECT TO BOTH POSITIVE AND NEGATIVE VOLTAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
11027789
|
Filing Dt:
|
12/29/2004
|
|
Title:
|
SYSTEM FOR SIGNAL ROUTING LINE AGGREGATION IN A FIELD-PROGRAMMABLE GATE ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2007
|
Application #:
|
11028471
|
Filing Dt:
|
12/31/2004
|
|
Title:
|
FIELD PROGRAMMABLE GATE ARRAY LONG LINE ROUTING NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
11056957
|
Filing Dt:
|
02/11/2005
|
|
Title:
|
TILEABLE FIELD-PROGRAMMABLE GATE ARRAY ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
11056983
|
Filing Dt:
|
02/11/2005
|
|
Title:
|
DEDICATED INPUT/OUTPUT FIRST IN/FIRST OUT MODULE FOR A FIELD PROGRAMMABLE GATE ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2007
|
Application #:
|
11056984
|
Filing Dt:
|
02/11/2005
|
|
Title:
|
BLOCK SYMMETRIZATION IN A FIELD PROGRAMMABLE GATE ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
11071127
|
Filing Dt:
|
03/03/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/01/2005
| | | | |
|
Title:
|
DEVICE FOR PROTECTING I/O LINES USING PIN OR NIP CONDUCTING LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSORS AND STEERING DIODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
11071128
|
Filing Dt:
|
03/03/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/15/2005
| | | | |
|
Title:
|
UNI-DIRECTIONAL PIN OR NIP CONDUCTING LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSORS AND STEERING DIODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2007
|
Application #:
|
11071513
|
Filing Dt:
|
03/03/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/01/2005
| | | | |
|
Title:
|
BI-DIRECTIONAL PIN OR NIP LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSORS AND STEERING DIODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
11074922
|
Filing Dt:
|
03/07/2005
|
|
Publication #:
|
|
Pub Dt:
|
07/07/2005
| | | | |
|
Title:
|
MULTI-LEVEL ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY HAVING TRANSMITTERS AND RECEIVERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2008
|
Application #:
|
11078952
|
Filing Dt:
|
03/10/2005
|
|
Title:
|
SWITCHING RATIO AND ON-STATE RESISTANCE OF AN ANTIFUSE PROGRAMMED BELOW 5 MA AND HAVING A TA OR TAN BARRIER METAL LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2012
|
Application #:
|
11079323
|
Filing Dt:
|
03/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
07/21/2005
| | | | |
|
Title:
|
METHOD OF FABRICATING A LIGHT-EMITTING DEVICE (LED) UTILIZING POWDER/PELLETIZED HOMOGENEOUSLY MIXED MOLDING COMPOUND
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11088621
|
Filing Dt:
|
03/23/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/25/2005
| | | | |
|
Title:
|
BLOCK LEVEL ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
11090246
|
Filing Dt:
|
03/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
|
Title:
|
FULL-BRIDGE AND HALF-BRIDGE COMPATIBLE DRIVER TIMING SCHEDULE FOR DIRECT DRIVE BACKLIGHT SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
11095294
|
Filing Dt:
|
03/31/2005
|
|
Title:
|
ZIGZAG TOPOLOGY FOR BALANCING CURRENT AMONG PARALLELED GAS DISCHARGE LAMPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
11095313
|
Filing Dt:
|
03/31/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
|
Title:
|
NESTED BALANCING TOPOLOGY FOR BALANCING CURRENT AMONG MULTIPLE LAMPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
11099995
|
Filing Dt:
|
04/06/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
|
Title:
|
PRIMARY SIDE CURRENT BALANCING SCHEME FOR MULTIPLE CCF LAMP OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
11120509
|
Filing Dt:
|
05/02/2005
|
|
Title:
|
REPEATABLE BLOCK PRODUCING A NON-UNIFORM ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY HAVING SEGMENTED TRACKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
11123733
|
Filing Dt:
|
05/05/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS OF MEMORY CLEARING WITH MONITORING RAM MEMORY CELLS IN A FIELD PROGRAMMABLE GATED ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
11123734
|
Filing Dt:
|
05/05/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
|
Title:
|
FIELD-PROGRAMMABLE GATE ARRAY LOW VOLTAGE DIFFERENTIAL SIGNALING DRIVER UTILIZING TWO COMPLIMENTARY OUTPUT BUFFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2007
|
Application #:
|
11128682
|
Filing Dt:
|
05/13/2005
|
|
Title:
|
CHIP CARRIER SUBSTRATE WITH A LAND GRID ARRAY AND EXTERNAL BOND TERMINALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
11128743
|
Filing Dt:
|
05/13/2005
|
|
Title:
|
METHOD FOR USING A CHIP CARRIER SUBSTRATE WITH A LAND GRID ARRAY AND EXTERNAL BOND TERMINALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
11145042
|
Filing Dt:
|
06/03/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
|
Title:
|
SPLIT-GATE POWER MODULE FOR SUPPRESSING OSCILLATION THEREIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2010
|
Application #:
|
11145877
|
Filing Dt:
|
06/06/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
|
Title:
|
DUAL-SLOPE BRIGHTNESS CONTROL FOR TRANSFLECTIVE DISPLAYS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
11152018
|
Filing Dt:
|
06/13/2005
|
|
Title:
|
NON-VOLATILE PROGRAMMABLE MEMORY CELL AND ARRAY FOR PROGRAMMABLE LOGIC ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2010
|
Application #:
|
11152019
|
Filing Dt:
|
06/13/2005
|
|
Title:
|
ISOLATED-NITRIDE-REGION NON-VOLATILE MEMORY CELL AND FABRICATION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
11154134
|
Filing Dt:
|
06/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
|
Title:
|
ADHESION AND/OR ENCAPSULATION OF SILICON CARBIDE-BASED SEMICONDUCTOR DEVICES ON CERAMIC SUBSTRATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2008
|
Application #:
|
11154488
|
Filing Dt:
|
06/16/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
|
Title:
|
SLOPE COMPENSATION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
11155005
|
Filing Dt:
|
06/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
|
Title:
|
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11171488
|
Filing Dt:
|
06/29/2005
|
|
Title:
|
ARCHITECTURE FOR FACE-TO-FACE BONDING BETWEEN SUBSTRATE AND MULTIPLE DAUGHTER CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
11171489
|
Filing Dt:
|
06/29/2005
|
|
Title:
|
METHOD FOR ERASING PROGRAMMABLE INTERCONNECT CELLS FOR FIELD PROGRAMMABLE GATE ARRAYS USING REVERSE BIAS VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
11171510
|
Filing Dt:
|
06/29/2005
|
|
Title:
|
INTEGRATED CIRCUIT WAFER WITH INTER-DIE METAL INTERCONNECT LINES TRAVERSING SCRIBE-LINE BOUNDARIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
11181503
|
Filing Dt:
|
07/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/26/2006
| | | | |
|
Title:
|
PUSH-PULL DRIVER WITH NULL-SHORT FEATURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
11181505
|
Filing Dt:
|
07/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
|
Title:
|
INCREMENTAL DISTRIBUTED DRIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
11181649
|
Filing Dt:
|
07/14/2005
|
|
Title:
|
RAMP GENERATOR WITH FAST RESET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
11183554
|
Filing Dt:
|
07/18/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
|
Title:
|
SHOOT-THROUGH PREVENTION CIRCUIT FOR PASSIVE LEVEL-SHIFTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2008
|
Application #:
|
11185426
|
Filing Dt:
|
07/19/2005
|
|
Title:
|
APPARATUS AND METHOD FOR REDUCING LEAKAGE OF UNUSED BUFFERS IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2009
|
Application #:
|
11185427
|
Filing Dt:
|
07/19/2005
|
|
Title:
|
METHOD FOR SECURE DELIVERY OF CONFIGURATION DATA FOR A PROGRAMMABLE LOGIC DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2009
|
Application #:
|
11187068
|
Filing Dt:
|
07/22/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/17/2005
| | | | |
|
Title:
|
FIELD PROGRAMMABLE GATE ARRAY AND MICROCONTROLLER SYSTEM-ON-A-CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
11189199
|
Filing Dt:
|
07/25/2005
|
|
Title:
|
DELAY LOCKED LOOP FOR AND FPGA ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2008
|
Application #:
|
11195002
|
Filing Dt:
|
08/01/2005
|
|
Title:
|
REPROGRAMMABLE METAL-TO-METAL ANTIFUSE EMPLOYING CARBON-CONTAINING ANTIFUSE MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
11202686
|
Filing Dt:
|
08/12/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/08/2005
| | | | |
|
Title:
|
ARCHITECTURE FOR ROUTING RESOURCES IN A FIELD PROGRAMMABLE GATE ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11210492
|
Filing Dt:
|
08/23/2005
|
|
Title:
|
AMORPHOUS CARBON METAL-TO-METAL ANTIFUSE WITH ADHESION PROMOTING LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
11219597
|
Filing Dt:
|
09/01/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR UNIVERSAL PROGRAM CONTROLLED BUS ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2009
|
Application #:
|
11233180
|
Filing Dt:
|
09/21/2005
|
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
|
Title:
|
RF POWER TRANSISTOR PACKAGE
|
|
