USPTO Assignments on the Web

	United States Patent and Trademark Office
	Home\|Site Index\|Search\|Guides\|Contacts\|eBusiness\|eBiz alerts\|News\|Help

Assignments on the Web > Patent Query

Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	033119/0615			Pages:	14
		Recorded:	06/10/2014
Attorney Dkt #:	RPXC-29189-CYPRESS SEMICO
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 88

Patent #:	5453957	Issue Dt:	09/26/1995	Application #:	08123377	Filing Dt:	09/17/1993
Title:	MEMORY ARCHITECTURE FOR BURST MODE ACCESS

Patent #:	5510638	Issue Dt:	04/23/1996	Application #:	08234288	Filing Dt:	04/28/1994
Title:	FIELD SHIELD ISOLATED EPROM

Patent #:	5559465	Issue Dt:	09/24/1996	Application #:	08283223	Filing Dt:	07/29/1994
Title:	OUTPUT PRECONDITIONING CIRCUIT WITH AN OUTPUT LEVEL LATCH AND A CLAMP

Patent #:	5625522	Issue Dt:	04/29/1997	Application #:	08297629	Filing Dt:	08/29/1994
Title:	APPARATUS FOR SMART POWER SUPPLY ESD PROTECTION STRUCTURE

Patent #:	5504443	Issue Dt:	04/02/1996	Application #:	08301657	Filing Dt:	09/07/1994
Title:	DIFFERENTIAL LATCH SENSE AMPLIFIERS USING FEEDBACK

Patent #:	5737612	Issue Dt:	04/07/1998	Application #:	08316121	Filing Dt:	09/30/1994
Title:	POWER-ON RESET CONTROL CIRCUIT

Patent #:	5502405	Issue Dt:	03/26/1996	Application #:	08335908	Filing Dt:	11/08/1994
Title:	METHOD AND APPARATUS FOR CML/ECL TO CMOS/TTL TRANSLATORS

Patent #:	5559447	Issue Dt:	09/24/1996	Application #:	08341371	Filing Dt:	11/17/1994
Title:	OUTPUT BUFFER WITH VARIABLE OUTPUT IMPEDANCE

Patent #:	5581216	Issue Dt:	12/03/1996	Application #:	08377269	Filing Dt:	01/24/1995
Title:	LOW JITTER VOLTAGE CONTROLLED OSCILLATOR (VCO) CIRCUIT

Patent #:	5453950	Issue Dt:	09/26/1995	Application #:	08377952	Filing Dt:	01/24/1995
Title:	FIVE TRANSISTOR MEMORY CELL WITH SHARED POWER LINE

Patent #:	5570043	Issue Dt:	10/29/1996	Application #:	08381125	Filing Dt:	01/31/1995
Title:	OVERVOLTAGE TOLERANT INTEGRATED CIRCUIT OUTPUT BUFFER

Patent #:	5563839	Issue Dt:	10/08/1996	Application #:	08413360	Filing Dt:	03/30/1995
Title:	SEMICONDUCTOR MEMORY DEVICE HAVING A SLEEP MODE

Patent #:	5644533	Issue Dt:	07/01/1997	Application #:	08427826	Filing Dt:	04/26/1995
Title:	FLASH MEMORY SYSTEM, AND METHODS OF CONSTRUCTING AND UTILIZING SAME

Patent #:	5604711	Issue Dt:	02/18/1997	Application #:	08446539	Filing Dt:	05/19/1995
Title:	LOW POWER HIGH VOLTAGE SWITCH WITH GATE BIAS CIRCUIT TO MINIMIZE POWER CONSUMPTION

Patent #:	5648669	Issue Dt:	07/15/1997	Application #:	08452217	Filing Dt:	05/26/1995
Title:	HIGH SPEED FLASH MEMORY CELL STRUCTURE AND METHOD

Patent #:	5831926	Issue Dt:	11/03/1998	Application #:	08473076	Filing Dt:	06/07/1995
Title:	MEMORY ARCHITECTURE FOR BURST MODE ACCESS

Patent #:	5565791	Issue Dt:	10/15/1996	Application #:	08498622	Filing Dt:	07/07/1995
Title:	METHOD AND APPARATUS FOR DISABLING UNUSED SENSE AMPLIFIERS

Patent #:	5621695	Issue Dt:	04/15/1997	Application #:	08502974	Filing Dt:	07/17/1995
Title:	SRAM WITH SIMPLIFIED ARCHITECTURE FOR USE WITH PIPELINED DATA

Patent #:	5572474	Issue Dt:	11/05/1996	Application #:	08503807	Filing Dt:	07/18/1995
Title:	PSEUDO-DIFFERENTIAL SENSE AMPLIFIER

Patent #:	5638322	Issue Dt:	06/10/1997	Application #:	08503988	Filing Dt:	07/19/1995
Title:	APPARATUS AND METHOD FOR IMPROVING COMMON MODE NOISE REJECTION IN PSEUDO-DIFFERENTIAL SENSE AMPLIFIERS

Patent #:	5654645	Issue Dt:	08/05/1997	Application #:	08507849	Filing Dt:	07/27/1995
Title:	BUFFER WITH CONTROLLED HYSTERESIS

Patent #:	5844271	Issue Dt:	12/01/1998	Application #:	08517495	Filing Dt:	08/21/1995
Title:	SINGLE LAYER POLYCRYSTALLINE SILICON SPLIT-GATE EEPROM CELL HAVING A BURIED CONTROL GATE

Patent #:	5654652	Issue Dt:	08/05/1997	Application #:	08534358	Filing Dt:	09/27/1995
Title:	HIGH-SPEED RATIO CMOS LOGIC STRUCTURE WITH STATIC AND DYNAMIC PULLUPS AND/OR PULLDOWNS USING FEEDBACK

Patent #:	5602776	Issue Dt:	02/11/1997	Application #:	08549483	Filing Dt:	10/27/1995
Title:	NON-VOLATILE, STATIC RANDOM ACCESS MEMORY WITH CURRENT LIMITING

Patent #:	5636161	Issue Dt:	06/03/1997	Application #:	08549919	Filing Dt:	10/30/1995
Title:	AN EPROM BIT-LINE INTERFACE FOR IMPLEMENTING PROGRAMMING, VERIFICATION AND TESTING

Patent #:	5740174	Issue Dt:	04/14/1998	Application #:	08552272	Filing Dt:	11/02/1995
Title:	METHOD AND APPARATUS FOR PERFORMING COLLISION DETECTION AND ARBITRATION WITHIN AN EXPANSION BUS HAVING MULTIPLE TRANSMISSION REPEATER UNITS

Patent #:	5712820	Issue Dt:	01/27/1998	Application #:	08559983	Filing Dt:	11/17/1995
Title:	MULTIPLE WORD WIDTH MEMORY ARRAY CLOCKING SCHEME

Patent #:	5656959	Issue Dt:	08/12/1997	Application #:	08562478	Filing Dt:	11/24/1995
Title:	CLOCK SYNTHESIZER DUAL FUNCTION PIN SYSTEM AND METHOD THEREFOR

Patent #:	5600267	Issue Dt:	02/04/1997	Application #:	08563350	Filing Dt:	11/28/1995
Title:	APPARATUS FOR A PROGRAMMABLE CML TO CMOS TRANSLATOR FOR POWER/SPEED ADJUSTMENT

Patent #:	5642318	Issue Dt:	06/24/1997	Application #:	08567544	Filing Dt:	12/05/1995
Title:	IMPROVED TESTING METHOD FOR FIFOS

Patent #:	5712992	Issue Dt:	01/27/1998	Application #:	08567893	Filing Dt:	12/06/1995
Title:	STATE MACHINE DESIGN FOR GENERATING EMPTY AND FULL FLAGS IN AN ASYNCHRONOUS FIFO

Patent #:	5809339	Issue Dt:	09/15/1998	Application #:	08567918	Filing Dt:	12/06/1995
Title:	STATE MACHINE DESIGN FOR GENERATING HALF-FULL AND HALF-EMPTY FLAGS IN AN ASYNCHRONOUS FIFO

Patent #:	5767713	Issue Dt:	06/16/1998	Application #:	08569682	Filing Dt:	12/08/1995
Title:	PHASE LOCKED LOOP HAVING INTEGRATION GAIN REDUCTION

Patent #:	5673234	Issue Dt:	09/30/1997	Application #:	08572181	Filing Dt:	12/13/1995
Title:	READ BITLINE WRITER FOR FALLTHRU IN FIFO'S

Patent #:	5627797	Issue Dt:	05/06/1997	Application #:	08572623	Filing Dt:	12/14/1995
Title:	FULL AND EMPTY FLAG GENERATOR FOR SYNCHRONOUS FIFOS

Patent #:	5903174	Issue Dt:	05/11/1999	Application #:	08575554	Filing Dt:	12/20/1995
Title:	METHOD AND APPARATUS FOR REDUCING SKEW AMONG INPUT SIGNALS WITHIN AN INTEGRATED CIRCUIT

Patent #:	5710905	Issue Dt:	01/20/1998	Application #:	08575985	Filing Dt:	12/21/1995
Title:	CACHE CONTROLLER FOR A NON-SYMETRIC CACHE SYSTEM

Patent #:	5835970	Issue Dt:	11/10/1998	Application #:	08576505	Filing Dt:	12/21/1995
Title:	BURST ADDRESS GENERATOR HAVING TWO MODES OF OPERATION EMPLOYING A LINEAR/NONLINEAR COUNTER USING DECODED ADDRESSES

Patent #:	5666069	Issue Dt:	09/09/1997	Application #:	08577258	Filing Dt:	12/22/1995
Title:	DATA OUTPUT STAGE INCORPORATING AN INVERTING OPERATIONAL AMPLIFIER

Patent #:	5850568	Issue Dt:	12/15/1998	Application #:	08577712	Filing Dt:	12/22/1995
Title:	CIRCUIT HAVING PLURALITY OF CARRY/SUM ADDERS HAVING READ COUNT, WRITE COUNT, AND OFFSET INPUTS TO GENERATE AN OUTPUT FLAG IN RESPONSE TO FIFO FULLNESS

Patent #:	5652732	Issue Dt:	07/29/1997	Application #:	08577716	Filing Dt:	12/22/1995
Title:	APPARATUS AND METHOD FOR MATCHING A CLOCK DELAY TO A DELAY THROUGH A MEMORY ARRAY

Patent #:	5640356	Issue Dt:	06/17/1997	Application #:	08578187	Filing Dt:	12/29/1995
Title:	TWO-STAGE DIFFERENTIAL SENSE AMPLIFIER WITH POSITIVE FEEDBACK IN THE FIRST AND SECOND STAGES

Patent #:	5852748	Issue Dt:	12/22/1998	Application #:	08578209	Filing Dt:	12/29/1995
Title:	PROGRAMMABLE READ-WRITE WORD LINE EQUALITY SIGNAL GENERATION FOR FIFOS

Patent #:	5799176	Issue Dt:	08/25/1998	Application #:	08578478	Filing Dt:	12/26/1995
Title:	METHOD AND APPARATUS FOR PROVIDING CLOCK SIGNALS TO MACROCELLS OF LOGIC DEVICES

Patent #:	5689471	Issue Dt:	11/18/1997	Application #:	08579079	Filing Dt:	12/22/1995
Title:	DUMMY CELL FOR PROVIDING A REFERENCE VOLTAGE IN A MEMORY ARRAY

Patent #:	6452927	Issue Dt:	09/17/2002	Application #:	08581242	Filing Dt:	12/29/1995
Title:	METHOD AND APPARATUS FOR PROVIDING A SERIAL INTERFACE BETWEEN AN ASYNCHRONOUS TRANSFER MODE (ATM) LAYER AND A PHYSICAL (PHY) LAYER

Patent #:	5784370	Issue Dt:	07/21/1998	Application #:	08581267	Filing Dt:	12/29/1995
Title:	METHOD AND APPARATUS FOR REGENERATING A CONTROL SIGNAL AT AN ASYNCHRONOUS TRANSFER MODE (ATM) LAYER OR A PHYSICAL (PHY) LAYER

Patent #:	5640523	Issue Dt:	06/17/1997	Application #:	08598157	Filing Dt:	02/07/1996
Title:	METHOD AND APPARATUS FOR A PULSED TRI-STATE PHASE DETECTOR FOR REDUCED JITTER CLOCK RECOVERY

Patent #:	5821794	Issue Dt:	10/13/1998	Application #:	08626043	Filing Dt:	04/01/1996
Title:	CLOCK DISTRIBUTION ARCHITECTURE AND METHOD FOR HIGH SPEED CPLDS

Patent #:	5656837	Issue Dt:	08/12/1997	Application #:	08633857	Filing Dt:	04/16/1996
Title:	FLASH MEMORY SYSTEM, AND METHODS OF CONSTRUCTING AND UTILIZING SAME

Patent #:	5963056	Issue Dt:	10/05/1999	Application #:	08661436	Filing Dt:	06/11/1996
Title:	FULL AND EMPTY FLAG GENERATOR FOR SYNCHRONOUS FIFOS

Patent #:	5844423	Issue Dt:	12/01/1998	Application #:	08666751	Filing Dt:	06/19/1996
Title:	HALF-FULL FLAG GENERATOR FOR SYNCHRONOUS FIFOS

Patent #:	5848066	Issue Dt:	12/08/1998	Application #:	08705990	Filing Dt:	08/29/1996
Title:	METHODS FOR MAXIMIZING ROUTABILITY IN A PROGRAMMABLE INTERCONNECT MATRIX HAVING LESS THAN FULL CONNECTABILITY

Patent #:	5787047	Issue Dt:	07/28/1998	Application #:	08745876	Filing Dt:	11/08/1996
Title:	MEMORY ARCHITECTURE FOR BURST MODE ACCESS

Patent #:	5784242	Issue Dt:	07/21/1998	Application #:	08758336	Filing Dt:	12/03/1996
Title:	APPARATUS FOR SMART POWER SUPPLY ESD PROTECTION STRUCTURE

Patent #:	5818272	Issue Dt:	10/06/1998	Application #:	08760304	Filing Dt:	12/04/1996
Title:	DIGITAL INTEGRATION GAIN REDUCTION METHOD

Patent #:	5949261	Issue Dt:	09/07/1999	Application #:	08767767	Filing Dt:	12/17/1996
Title:	METHOD AND CIRCUIT FOR REDUCING POWER AND/OR CURRENT CONSUMPTION

Patent #:	6005795	Issue Dt:	12/21/1999	Application #:	08789299	Filing Dt:	01/30/1997
Title:	SINGLE ENDED DUAL PORT MEMORY CELL

Patent #:	6005796	Issue Dt:	12/21/1999	Application #:	08789300	Filing Dt:	01/30/1997
Title:	SINGLE ENDED SIMPLER DUAL PORT MEMORY CELL

Patent #:	5864251	Issue Dt:	01/26/1999	Application #:	08791002	Filing Dt:	01/27/1997
Title:	METHOD AND APPARATUS FOR SELF-RESETTING LOGIC CIRCUITRY

Patent #:	5760438	Issue Dt:	06/02/1998	Application #:	08800656	Filing Dt:	02/04/1997
Title:	HIGH SPEED FLASH MEMORY CELL STRUCTURE AND METHOD

Patent #:	5896069	Issue Dt:	04/20/1999	Application #:	08815701	Filing Dt:	03/12/1997
Title:	CROSS COUPLED DIFFERENTIAL OSCILLATOR

Patent #:	6380762	Issue Dt:	04/30/2002	Application #:	08824634	Filing Dt:	03/27/1997
Title:	MULTI-LEVEL PROGRAMMABLE VOLTAGE CONTROL AND OUTPUT BUFFER WITH SELECTABLE OPERATING VOLTAGE

Patent #:	5862092	Issue Dt:	01/19/1999	Application #:	08852837	Filing Dt:	05/07/1997
Title:	READ BITLINE WRITER FOR FALLTHRU IN FIFO'S

Patent #:	5867448	Issue Dt:	02/02/1999	Application #:	08873005	Filing Dt:	06/11/1997
Title:	BUFFER FOR MEMORY MODULES WITH TRACE DELAY COMPENSATION

Patent #:	5933032	Issue Dt:	08/03/1999	Application #:	08897375	Filing Dt:	07/21/1997
Title:	APPARATUS AND METHOD FOR GENERATING A PULSE SIGNAL

Patent #:	6515505	Issue Dt:	02/04/2003	Application #:	08902206	Filing Dt:	07/29/1997
Title:	BOND OPTION DECODING

Patent #:	6016403	Issue Dt:	01/18/2000	Application #:	08911132	Filing Dt:	08/14/1997
Title:	STATE MACHINE DESIGN FOR GENERATING EMPTY AND FULL FLAGS IN AN ASYNCHRONOUS FIFO

Patent #:	5809312	Issue Dt:	09/15/1998	Application #:	08920124	Filing Dt:	09/02/1997
Title:	POWER-ON RESET CONTROL CIRCUIT

Patent #:	5805003	Issue Dt:	09/08/1998	Application #:	08921420	Filing Dt:	08/29/1997
Title:	CLOCK FREQUENCY SYNTHESIS USING DELAY-LOCKED LOOP

Patent #:	5880997	Issue Dt:	03/09/1999	Application #:	08939463	Filing Dt:	09/29/1997
Title:	BUBBLEBACK FOR FIFOS

Patent #:	5994920	Issue Dt:	11/30/1999	Application #:	08955809	Filing Dt:	10/22/1997
Title:	HALF-FULL FLAG GENERATOR FOR SYNCHRONOUS FIFOS

Patent #:	6043684	Issue Dt:	03/28/2000	Application #:	08960584	Filing Dt:	10/29/1997
Title:	METHOD AND APPARATUS FOR REDUCING SKEW BETWEEN INPUT SIGNALS AND CLOCK SIGNALS WITHIN AN INTEGRATED CIRCUIT

Patent #:	5930176	Issue Dt:	07/27/1999	Application #:	09013499	Filing Dt:	01/26/1998
Title:	MULTIPLE WORD WIDTH MEMORY ARRAY CLOCKING SCHEME

Patent #:	5991834	Issue Dt:	11/23/1999	Application #:	09144301	Filing Dt:	08/31/1998
Title:	STATE MACHINE DESIGN FOR GENERATING HALF-FULL AND HALF-EMPTY FLAGS IN AN ASYNCHRONOUS FIFO

Patent #:	6243664	Issue Dt:	06/05/2001	Application #:	09181084	Filing Dt:	10/27/1998
Title:	METHODS FOR MAXIMIZING ROUTABILITY IN A PROGRAMMABLE INTERCONNECT MATRIX HAVING LESS THAN FULL CONNECTABILITY

Patent #:	6070203	Issue Dt:	05/30/2000	Application #:	09201413	Filing Dt:	11/30/1998
Title:	CIRCUIT FOR GENERATING ALMOST FULL AND ALMOST EMPTY FLAGS IN RESPONCE TO SUM AND CARRY OUTPUTS IN ASYNCHRONOUS AND SYNCHRONOUS FIFOS

Patent #:	6411140	Issue Dt:	06/25/2002	Application #:	09307063	Filing Dt:	05/07/1999
Title:	METHOD AND APPARATUS FOR REDUCING SKEW BETWEEN INPUT SIGNALS AND CLOCK SIGNALS WITHIN AN INTEGRATED CIRCUIT

Patent #:	6222393	Issue Dt:	04/24/2001	Application #:	09357474	Filing Dt:	07/20/1999
Title:	APPARATUS AND METHOD FOR GENERATING A PULSE SIGNAL

Patent #:	6326853	Issue Dt:	12/04/2001	Application #:	09383328	Filing Dt:	08/26/1999
Title:	CIRCUITRY, ARCHITECTURE AND METHOD(S) FOR PHASE MATCHING AND/OR REDUCING LOAD CAPACITANCE, CURRENT AND/OR POWER CONSUMPTION IN AN OSCILLATOR

Patent #:	NONE	Issue Dt:		Application #:	09391135	Filing Dt:	09/07/1999
Publication #:	US20020000846	Pub Dt:	01/03/2002
Title:	METHOD AND CIRCUIT FOR REDUCING POWER AND/OR CURRENT CONSUMPTION

Patent #:	6262912	Issue Dt:	07/17/2001	Application #:	09443062	Filing Dt:	11/18/1999
Title:	SINGLE ENDED SIMPLEX DUAL PORT MEMORY CELL

Patent #:	6181595	Issue Dt:	01/30/2001	Application #:	09443126	Filing Dt:	11/18/1999
Title:	SINGLE ENDED DUAL PORT MEMORY CELL

Patent #:	6731566	Issue Dt:	05/04/2004	Application #:	09876429	Filing Dt:	06/06/2001
Title:	SINGLE ENDED SIMPLEX DUAL PORT MEMORY CELL

Patent #:	6377128	Issue Dt:	04/23/2002	Application #:	09966603	Filing Dt:	09/28/2001
Title:	Circuitry, architecture and method (s) for phase matching and/or reducing load capacitance, current and/or power consumption in an oscillator

Patent #:	6670852	Issue Dt:	12/30/2003	Application #:	09981448	Filing Dt:	10/17/2001
Title:	OSCILLATOR TUNING METHOD

Patent #:	6664810	Issue Dt:	12/16/2003	Application #:	10043785	Filing Dt:	10/26/2001
Title:	MULTI-LEVEL PROGRAMMABLE VOLTAGE CONTROL AND OUTPUT BUFFER WITH SELECTABLE OPERATING VOLTAGE

Patent #:	6593785	Issue Dt:	07/15/2003	Application #:	10133851	Filing Dt:	04/26/2002
Title:	METHOD AND CIRCUIT FOR REDUCING POWER AND/OR CURRENT CONSUMPTION

Assignor

CYPRESS SEMICONDUCTOR CORPORATION

Exec Dt:

06/04/2014

Assignee

RPX CORPORATION

ONE MARKET PLAZA, STEUART TOWER, SUITE 800

SAN FRANCISCO, CALIFORNIA 94105

Correspondence name and address
	GREGORY M. HOWISON
	P.O. BOX 741715
	DALLAS, TX 75374-1715

Search Results as of: 05/25/2024 09:16 AM

If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6

Web interface last modified: August 25, 2017 v.2.6