Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 021096/0616 | |
| Pages: | 2 |
| | Recorded: | 06/16/2008 | | |
| Attorney Dkt #: | 135-G001 (CONF ASGN 951) |
| Conveyance: | CONFIRMATORY ASSIGNMENT CONFIRMING THE PREVIOUS ASSIGNMENT RECORDED AT REEL 009996 FRAME 0392, AND DISCLAIMING ANY RIGHT, TITLE, AND INTEREST. |
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Total properties:
1
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Patent #:
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Issue Dt:
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09/26/1995
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Application #:
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08297723
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Filing Dt:
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08/26/1994
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Title:
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FAST VOLTAGE EQUILIBRATION OF COMPLEMENTARY DATA LINES FOLLOWING WRITE CYCLE IN MEMORY CIRCUITS
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Assignee
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| 20765 PHOENIX LAKE ROAD |
| SONORA, CALIFORNIA 95370 |
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Correspondence name and address
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ANDREW C. GRAHAM
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7600B N. CAPITAL OF TEXAS HWY.
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SUITE 350
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AUSTIN, TX 78731
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