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Total properties:
17
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Patent #:
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Issue Dt:
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01/31/2006
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Application #:
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10118242
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Filing Dt:
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04/09/2002
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Publication #:
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Pub Dt:
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10/09/2003
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Title:
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APPARATUS AND METHOD FOR HANDLING OF MULTI-LEVEL CIRCUIT DESIGN DATA
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Patent #:
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Issue Dt:
|
10/02/2007
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Application #:
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10172996
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Filing Dt:
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06/18/2002
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Publication #:
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Pub Dt:
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12/18/2003
| | | | |
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Title:
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METHOD FOR DETECTING BUS CONTENTION FROM RTL DESCRIPTION
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Patent #:
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Issue Dt:
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04/05/2005
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Application #:
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10217535
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Filing Dt:
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08/14/2002
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Publication #:
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Pub Dt:
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02/19/2004
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Title:
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METHOD FOR DETERMINING FAULT COVERAGE FROM RTL DESCRIPTION
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Patent #:
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Issue Dt:
|
07/11/2006
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Application #:
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10631755
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Filing Dt:
|
08/01/2003
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Publication #:
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Pub Dt:
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02/03/2005
| | | | |
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Title:
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IDENTIFICATION AND IMPLEMENTATION OF CLOCK GATING IN THE DESIGN OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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10695803
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Filing Dt:
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10/30/2003
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Publication #:
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Pub Dt:
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05/05/2005
| | | | |
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Title:
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METHOD FOR CLOCK SYNCHRONIZATION VALIDATION IN INTEGRATED CIRCUIT DESIGN
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|
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Patent #:
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|
Issue Dt:
|
03/25/2008
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Application #:
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10711493
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Filing Dt:
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09/21/2004
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Publication #:
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Pub Dt:
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03/23/2006
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Title:
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A METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR GENERATING AND VERIFYING ISOLATION LOGIC MODULES IN DESIGN OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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12/19/2006
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Application #:
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10711971
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Filing Dt:
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10/15/2004
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Publication #:
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Pub Dt:
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04/20/2006
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Title:
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A METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR AUTOMATIC INSERTION AND CORRECTNESS VERIFICATION OF LEVEL SHIFTERS IN INTEGRATED CIRCUITS WITH MULTIPLE VOLTAGE DOMAINS
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Patent #:
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|
Issue Dt:
|
05/08/2007
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Application #:
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10783091
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Filing Dt:
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02/23/2004
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Publication #:
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Pub Dt:
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05/19/2005
| | | | |
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Title:
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PATTERN RECOGNITION IN AN INTEGRATED CIRCUIT DESIGN
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|
|
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
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10906571
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Filing Dt:
|
02/24/2005
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Publication #:
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|
Pub Dt:
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08/24/2006
| | | | |
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Title:
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A Method for Automatic Recognition of Handshake Data Exchange at Clock-Domain Crossing in Integrated Circuit Design
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|
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Patent #:
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|
Issue Dt:
|
06/09/2009
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Application #:
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11419624
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Filing Dt:
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05/22/2006
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Publication #:
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Pub Dt:
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11/02/2006
| | | | |
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Title:
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A METHOD OF OPTIMIZATION OF CLOCK GATING IN INTEGRATED CIRCUIT DESIGNS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
11/11/2008
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Application #:
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11423919
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Filing Dt:
|
06/13/2006
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|
Publication #:
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|
Pub Dt:
|
12/14/2006
| | | | |
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Title:
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BUS REPRESENTATION FOR EFFICIENT PHYSICAL SYNTHESIS OF INTEGRATED CIRCUIT DESIGNS
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|
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Patent #:
|
|
Issue Dt:
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05/19/2009
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Application #:
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11426936
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Filing Dt:
|
06/27/2006
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|
Publication #:
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Pub Dt:
|
01/10/2008
| | | | |
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Title:
|
METHOD FOR RECOGNIZING AND VERIFYING FIFO STRUCTURES IN INTEGRATED CIRCUIT DESIGNS
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|
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11676232
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Filing Dt:
|
02/16/2007
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|
Publication #:
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|
Pub Dt:
|
08/21/2008
| | | | |
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Title:
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METHOD FOR GENERATING TIMING EXCEPTIONS
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|
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
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11692949
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Filing Dt:
|
03/29/2007
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|
Publication #:
|
|
Pub Dt:
|
10/02/2008
| | | | |
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Title:
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METHOD FOR ACCELERATING THE GENERATION OF AN OPTIMIZED GATE-LEVEL REPRESENTATION FROM A RTL REPRESENTATION
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|
|
|
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Patent #:
|
|
Issue Dt:
|
01/19/2010
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Application #:
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11749090
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Filing Dt:
|
05/15/2007
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|
Publication #:
|
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Pub Dt:
|
11/20/2008
| | | | |
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Title:
|
METHOD FOR MODELING AND VERIFYING TIMING EXCEPTIONS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
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Application #:
|
11755764
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Filing Dt:
|
05/31/2007
|
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
|
Title:
|
METHOD FOR CHECKING CONSTRAINTS EQUIVALENCE OF AN INTEGRATED CIRCUIT DESIGN
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
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Application #:
|
11837174
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Filing Dt:
|
08/10/2007
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2009
| | | | |
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Title:
|
METHOD FOR COMPUTING POWER SAVINGS AND DETERMINING THE PREFERRED CLOCK GATING CIRCUIT OF AN INTEGRATED CIRCUIT DESIGN
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|
