|
Total properties:
40
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/1995
|
Application #:
|
07928552
|
Filing Dt:
|
08/11/1992
|
|
Title:
|
MEMORY CONTROLLER AND METHOD DETERMINING EMPTY/FULL STATUS OF A FIFO MEMORY USING GRAY CODE COUNTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/1995
|
Application #:
|
08059029
|
Filing Dt:
|
05/06/1993
|
|
Title:
|
BURST-MODE DRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/1997
|
Application #:
|
08448003
|
Filing Dt:
|
05/23/1995
|
|
Title:
|
RESOURCE ALLOCATION WITH PARAMETER COUNTER IN MULTIPLE REQUESTER SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/1998
|
Application #:
|
08489489
|
Filing Dt:
|
06/12/1995
|
|
Title:
|
PARTITIONED DECOMPRESSION OF AUDIO DATA USING AUDIO DECODER ENGINE FOR COMPUTATIONALLY INTENSIVE PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/1998
|
Application #:
|
08612691
|
Filing Dt:
|
03/08/1996
|
|
Title:
|
SIGMA-DELTA DIGITAL-TO-ANALOG CONVERSION SYSTEM AND PROCESS THROUGH RECONSTRUCTION AND RESAMPLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/1999
|
Application #:
|
08616835
|
Filing Dt:
|
03/15/1996
|
|
Title:
|
MIXED VOLTAGE, MULTI-RAIL, HIGH DRIVE, LOW NOISE, ADJUSTABLE SLEW INPUT/OUTPUT BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/1999
|
Application #:
|
08801002
|
Filing Dt:
|
02/19/1997
|
|
Title:
|
VOLTAGE TOLERANT INPUT/OUTPUT BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/1999
|
Application #:
|
08813343
|
Filing Dt:
|
03/07/1997
|
|
Title:
|
TRANSFORMERLESS DATA ACCESS ARRANGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2000
|
Application #:
|
08899355
|
Filing Dt:
|
07/23/1997
|
|
Title:
|
METHOD OF EMBEDDING PAGE ADDRESS TRANSLATION ENTRIES WITHIN A SEQUENTIALLY ACCESSED DIGITAL AUDIO DATA STREAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08900084
|
Filing Dt:
|
07/24/1997
|
|
Title:
|
VOLTAGE TOLERANT BUS HOLD LATCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1999
|
Application #:
|
08926174
|
Filing Dt:
|
09/09/1997
|
|
Title:
|
SYSTEM AND METHOD FOR A MIXED VOLTAGE DRIVE SYSTEM FOR FLOATING SUBSTRATE TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/1999
|
Application #:
|
08956710
|
Filing Dt:
|
10/23/1997
|
|
Title:
|
MULTIPLE-PORT RING BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
08974073
|
Filing Dt:
|
11/19/1997
|
|
Title:
|
VOLTAGE TOLERANT BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2000
|
Application #:
|
08991392
|
Filing Dt:
|
12/16/1997
|
|
Title:
|
PROCESSOR HAVING MULTIPLE DATAPATH INSTANCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2000
|
Application #:
|
09005077
|
Filing Dt:
|
01/09/1998
|
|
Title:
|
OUTPUT BUFFER CIRCUIT AND METHOD THAT COMPENSATE FOR OPERATING CONDITIONS AND MANUFACTURING PROCESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09020152
|
Filing Dt:
|
02/06/1998
|
|
Title:
|
FAST ADDER/SUBTRACTOR FOR SIGNED FLOATING POINT NUMBERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09039283
|
Filing Dt:
|
03/12/1998
|
|
Title:
|
MULTIPLE MODE ANALOG JOYSTICK INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09039973
|
Filing Dt:
|
03/16/1998
|
|
Publication #:
|
|
Pub Dt:
|
12/13/2001
| | | | |
|
Title:
|
MODIFYING CIRCUIT DESIGNS RUNNING FROM BOTH EDGES OF CLOCK TO RUN FROM POSITIVE DESIGNS RUNNING FROM BOTH EDGES OF CLOCK TO RUN FROM POSITIVE EDGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
09053555
|
Filing Dt:
|
04/01/1998
|
|
Title:
|
VOLTAGE LEVEL SHIFT SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09075350
|
Filing Dt:
|
05/08/1998
|
|
Title:
|
MULTIPLE INPUT SIGNATURE TESTING & DIAGNOSIS FOR EMBEDDED BLOCKS IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
09088645
|
Filing Dt:
|
06/01/1998
|
|
Title:
|
TUNABLE DIGITAL OSCILLATOR CIRCUIT AND METHOD FOR PRODUCING CLOCK SIGNALS OF DIFFERENT FREQUENCIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09088754
|
Filing Dt:
|
06/02/1998
|
|
Title:
|
EDGE-TRIGGERED SCAN FLIP-FLOP AND ONE-PASS SCAN SYNTHESIS METHODOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
09099630
|
Filing Dt:
|
06/18/1998
|
|
Title:
|
USING POWER-ON MODE TO CONTROL TEST MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2001
|
Application #:
|
09103757
|
Filing Dt:
|
06/24/1998
|
|
Title:
|
EFFICIENT ROUTING FROM MULTIPLE SOURCES TO EMBEDDED DRAM AND OTHER LARGE CIRCUIT BLOCKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09104049
|
Filing Dt:
|
06/24/1998
|
|
Title:
|
HYBRID CIRCUIT MODEL SIMULATOR FOR ACCURATE TIMING AND NOISE ANALYSIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2000
|
Application #:
|
09128220
|
Filing Dt:
|
08/03/1998
|
|
Title:
|
SYSTEM AND METHOD FOR EFFICIENTLY TRANSFERRING INFORMATION BETWEEN PROCESSORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2000
|
Application #:
|
09149549
|
Filing Dt:
|
09/08/1998
|
|
Title:
|
VERTICALLY STACKABLE INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
09225650
|
Filing Dt:
|
01/05/1999
|
|
Title:
|
VOLTAGE TOLERANT INPUT/OUTPUT BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2000
|
Application #:
|
09252638
|
Filing Dt:
|
02/19/1999
|
|
Title:
|
MULTIPLE-PORT RING BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09285320
|
Filing Dt:
|
04/02/1999
|
|
Title:
|
DIFFERENTIAL CHARGE PUMP WITH LOW VOLTAGE COMMON MODE FEEDBACK CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09320191
|
Filing Dt:
|
05/26/1999
|
|
Title:
|
SKEW-INDEPENDENT MEMORY ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09326161
|
Filing Dt:
|
06/04/1999
|
|
Title:
|
SINGLE RAIL DOMINO LOGIC FOR FOUR-PHASE CLOCKING SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09676460
|
Filing Dt:
|
09/29/2000
|
|
Title:
|
READ DATA VALID LOOP-BACK FOR HIGH SPEED SYNCHRONIZED DRAM CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2002
|
Application #:
|
09729869
|
Filing Dt:
|
12/05/2000
|
|
Title:
|
System and method for efficiently implementing a double data rate memory architecture
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
09747351
|
Filing Dt:
|
12/19/2000
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2002
| | | | |
|
Title:
|
Enabling protected digital media to be shared between playback devices
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
09773956
|
Filing Dt:
|
01/31/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/01/2002
| | | | |
|
Title:
|
Method and apparatus for parametrically sorting music files
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
09783244
|
Filing Dt:
|
02/13/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/15/2002
| | | | |
|
Title:
|
Ensuring legitimacy of digital media
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2001
|
Application #:
|
29125073
|
Filing Dt:
|
06/15/2000
|
|
Title:
|
Audio player apparatus
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
29129604
|
Filing Dt:
|
09/18/2000
|
|
Title:
|
Server enclosure
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2001
|
Application #:
|
29131132
|
Filing Dt:
|
10/13/2000
|
|
Title:
|
Audio player apparatus
|
|
