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Reel/Frame:048586/0650   Pages: 3
Recorded: 03/13/2019
Attorney Dkt #:AMS001US
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
12/15/2020
Application #:
16250424
Filing Dt:
01/17/2019
Publication #:
Pub Dt:
09/19/2019
Title:
Adjustable Integrated Circuits and Methods for Designing the Same
Assignor
1
Exec Dt:
03/08/2019
Assignee
1
1735 TECHNOLOGY DRIVE
SUITE 420
SAN JOSE, CALIFORNIA 95110
Correspondence name and address
SILICON VALLEY PATENT GROUP LLP
4010 MOOORPARK AVE.
SUITE 210
SAN JOSE, CA 95117

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