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Total properties:
19
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Patent #:
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Issue Dt:
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06/13/1995
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Application #:
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08012266
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Filing Dt:
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02/01/1993
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Title:
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SYNCHRONOUS READ CHANNEL
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Patent #:
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Issue Dt:
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12/10/1996
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Application #:
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08341723
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Filing Dt:
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11/17/1994
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Title:
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DECIMATION DC OFFSET CONTROL IN A SAMPLED AMPLITUDE READ CHANNEL
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Patent #:
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Issue Dt:
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12/08/1998
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Application #:
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08399095
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Filing Dt:
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03/03/1995
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Title:
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MEMORY MAPPING DEFECT MANAGEMENT TECHNIQUE FOR AUTOMATIC TRACK PROCESSING WITHOUT ID FIELD
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Patent #:
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Issue Dt:
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12/09/1997
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Application #:
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08440508
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Filing Dt:
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05/12/1995
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Title:
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SAMPLED AMPLITUDE READ CHANNEL EMPLOYING INTERPOLATED TIMING RECOVERY
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Patent #:
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Issue Dt:
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05/13/1997
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Application #:
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08468108
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Filing Dt:
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06/06/1995
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Title:
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ERROR CORRECTION VERIFICATION METHOD AND APPARATUS USING CRC CHECK REMINDERS
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Patent #:
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Issue Dt:
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02/10/1998
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Application #:
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08681692
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Filing Dt:
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07/29/1996
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Title:
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A RATE 16/17 ENDEC WITH INDEPENDENT HIGH/LOW BYTE DECODING
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Patent #:
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Issue Dt:
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11/17/1998
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Application #:
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08681693
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Filing Dt:
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07/29/1996
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Title:
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CODING TO IMPROVE TIMING RECOVERY IN A SAMPLED AMPLITUDE READ CHANNEL
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08751880
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Filing Dt:
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11/18/1996
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Title:
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ZERO PHASE RESTART FOR INTERPOLATED TIMING RECOVERY IN A SAMPLED AMPLITUDE READ CHANNEL
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Patent #:
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Issue Dt:
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12/01/1998
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Application #:
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08820926
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Filing Dt:
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03/19/1997
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Title:
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SYNCHRONOUS READ CHANNEL EMPLOYING A DATA RANDOMIZER
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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08821174
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Filing Dt:
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03/19/1997
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Title:
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SYNCHRONOUS READ CHANNEL INTEGRATED CIRCUIT EMPLOYING A CHANNEL QUALITY CIRCUIT FOR CALIBRATION
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Patent #:
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Issue Dt:
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12/01/1998
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Application #:
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08821175
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Filing Dt:
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03/19/1997
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Title:
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SYNCHRONOUS READ CHANNEL EMPLOYING A SEQUENCE DETECTOR WITH PROGRAMMABLE DETECTOR LEVELS
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Patent #:
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Issue Dt:
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11/23/1999
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Application #:
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08822173
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Filing Dt:
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03/21/1997
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Title:
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SYCHRONOUS READ CHANNEL EMPLOYING REAL TIME DC OFFSET CONTROL
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Patent #:
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Issue Dt:
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04/11/2000
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Application #:
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08842146
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Filing Dt:
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04/23/1997
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Title:
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ERROR CORRECTION AND CONCURRENT VERIFICATION OF A PRODUCT CODE
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Patent #:
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Issue Dt:
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10/12/1999
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Application #:
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08859980
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Filing Dt:
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05/21/1997
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Title:
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ASYNCHRONOUS/SYNCHRONOUS DIGITAL GAIN CONTROL LOOP IN A SAMPLED AMPLITUDE READ CHANNEL
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Patent #:
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Issue Dt:
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12/01/1998
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Application #:
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08950880
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Filing Dt:
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10/15/1997
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Title:
|
RATE 16/17 ENDEC WITH INDEPENDENT HIGH/LOW BYTE DECODING
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Patent #:
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Issue Dt:
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11/23/1999
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Application #:
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08970600
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Filing Dt:
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11/14/1997
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Title:
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CONCURRENT GENERATION OF ECC ERROR SYNDROMES AND CRC VALIDATION SYNDROMES IN A DVD STORAGE DEVICE
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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08970730
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Filing Dt:
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11/14/1997
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Title:
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ECC SYSTEM EMPLOYING A DATA BUFFER FOR STORING CODEWORD DATA AND A SYNDROME BUFFER FOR STORING ERROR SYNDROMES
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Patent #:
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Issue Dt:
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05/27/2008
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Application #:
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10028871
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Filing Dt:
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12/21/2001
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Publication #:
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Pub Dt:
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06/20/2002
| | | | |
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Title:
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SYNCHRONOUS READ CHANNEL
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|
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Patent #:
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Issue Dt:
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06/07/2011
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Application #:
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12126188
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Filing Dt:
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05/23/2008
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Publication #:
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Pub Dt:
|
11/20/2008
| | | | |
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Title:
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SYNCHRONOUS READ CHANNEL
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