Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 019193/0658 | |
| Pages: | 10 |
| | Recorded: | 04/12/2007 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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11/21/2006
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Application #:
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10871311
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Filing Dt:
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06/18/2004
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Publication #:
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Pub Dt:
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03/10/2005
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Title:
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DEVELOPMENT SYSTEM FOR AN INTEGRATED CIRCUIT HAVING STANDARDIZED HARDWARE OBJECTS
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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10871329
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Filing Dt:
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06/18/2004
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Publication #:
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Pub Dt:
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01/20/2005
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Title:
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SYSTEM OF HARDWARE OBJECTS
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Patent #:
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Issue Dt:
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04/17/2007
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Application #:
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10871347
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Filing Dt:
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06/18/2004
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Publication #:
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Pub Dt:
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01/06/2005
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Title:
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DATA INTERFACE REGISTER STRUCTURE WITH REGISTERS FOR DATA, VALIDITY, GROUP MEMBERSHIP INDICATOR, AND READY TO ACCEPT NEXT MEMBER SIGNAL
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Patent #:
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Issue Dt:
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08/05/2008
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Application #:
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11326701
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Filing Dt:
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01/06/2006
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Publication #:
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Pub Dt:
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06/01/2006
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Title:
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ASYNCHRONOUS COMMUNICATION AMONG HARDWARE OBJECT NODES IN IC WITH RECEIVE AND SEND PORTS PROTOCOL REGISTERS USING TEMPORARY REGISTER BYPASS SELECT FOR VALIDITY INFORMATION
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Assignee
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| 3003 TASMAN DRIVE |
| SANTA CLARA, CALIFORNIA 95054 |
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Correspondence name and address
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KIRK A. MOORE
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1001 SW 5TH AVENUE, 16TH FLOOR
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PORTLAND, OREGON 97204
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