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Reel/Frame:045593/0662   Pages: 6
Recorded: 04/19/2018
Attorney Dkt #:075803.000002
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 32
1
Patent #:
9612844
Issue Dt:
04/04/2017
Application #:
13138176
Filing Dt:
09/20/2011
Publication #:
US20120124338
Pub Dt:
05/17/2012
Title:
SCHEDULING EXECUTION OF INSTRUCTIONS ON A PROCESSOR HAVING MULTIPLE HARDWARE THREADS WITH DIFFERENT EXECUTION RESOURCES
2
Patent #:
9658962
Issue Dt:
05/23/2017
Application #:
14153223
Filing Dt:
01/13/2014
Publication #:
US20140325159
Pub Dt:
10/30/2014
Title:
CONTROL OF PRE-FETCH TRAFFIC
3
Patent #:
NONE
Issue Dt:
Application #:
14456873
Filing Dt:
08/11/2014
Publication #:
US20150058574
Pub Dt:
02/26/2015
Title:
Increasing The Efficiency of Memory Resources In a Processor
4
Patent #:
NONE
Issue Dt:
Application #:
14548041
Filing Dt:
11/19/2014
Publication #:
US20150154022
Pub Dt:
06/04/2015
Title:
Soft-Partitioning of a Register File Cache
5
Patent #:
9870225
Issue Dt:
01/16/2018
Application #:
14572186
Filing Dt:
12/16/2014
Publication #:
US20150178076
Pub Dt:
06/25/2015
Title:
PROCESSOR WITH VIRTUALIZED INSTRUCTION SET ARCHITECTURE & METHODS
6
Patent #:
10642501
Issue Dt:
05/05/2020
Application #:
14589693
Filing Dt:
01/05/2015
Title:
HARDWARE VIRTUALIZED INPUT OUTPUT MEMORY MANAGEMENT UNIT
7
Patent #:
9652240
Issue Dt:
05/16/2017
Application #:
14596407
Filing Dt:
01/14/2015
Publication #:
US20150205611
Pub Dt:
07/23/2015
Title:
STACK POINTER VALUE PREDICTION
8
Patent #:
9934039
Issue Dt:
04/03/2018
Application #:
14598415
Filing Dt:
01/16/2015
Publication #:
US20150205612
Pub Dt:
07/23/2015
Title:
Stack Saved Variable Pointer Value Prediction
9
Patent #:
9361242
Issue Dt:
06/07/2016
Application #:
14608630
Filing Dt:
01/29/2015
Publication #:
US20150220450
Pub Dt:
08/06/2015
Title:
Return Stack Buffer Having Multiple Address Slots Per Stack Entry
10
Patent #:
9424203
Issue Dt:
08/23/2016
Application #:
14608745
Filing Dt:
01/29/2015
Publication #:
US20150220451
Pub Dt:
08/06/2015
Title:
Storing Look-Up Table Indexes in a Return Stack Buffer
11
Patent #:
NONE
Issue Dt:
Application #:
14612069
Filing Dt:
02/02/2015
Publication #:
US20150227371
Pub Dt:
08/13/2015
Title:
Processors with Support for Compact Branch Instructions & Methods
12
Patent #:
NONE
Issue Dt:
Application #:
14612077
Filing Dt:
02/02/2015
Publication #:
US20150227366
Pub Dt:
08/13/2015
Title:
PROCESSOR WITH GRANULAR ADD IMMEDIATES CAPABILITY & METHODS
13
Patent #:
10768930
Issue Dt:
09/08/2020
Application #:
14612104
Filing Dt:
02/02/2015
Publication #:
US20150227365
Pub Dt:
08/13/2015
Title:
PROCESSOR SUPPORTING ARITHMETIC INSTRUCTIONS WITH BRANCH ON OVERFLOW & METHODS
14
Patent #:
9830275
Issue Dt:
11/28/2017
Application #:
14715117
Filing Dt:
05/18/2015
Publication #:
US20160342523
Pub Dt:
11/24/2016
Title:
TRANSLATION LOOKASIDE BUFFER
15
Patent #:
9898293
Issue Dt:
02/20/2018
Application #:
14722292
Filing Dt:
05/27/2015
Publication #:
US20150347144
Pub Dt:
12/03/2015
Title:
Decoding Instructions That Are Modified By One Or More Other Instructions
16
Patent #:
10423417
Issue Dt:
09/24/2019
Application #:
14741738
Filing Dt:
06/17/2015
Publication #:
US20160321078
Pub Dt:
11/03/2016
Title:
Fault Tolerant Processor for Real-Time Systems
17
Patent #:
10048967
Issue Dt:
08/14/2018
Application #:
14798841
Filing Dt:
07/14/2015
Publication #:
US20160011869
Pub Dt:
01/14/2016
Title:
PROCESSOR ARRANGED TO OPERATE AS A SINGLE-THREADED (NX)-BIT PROCESSOR AND AS AN N-THREADED X-BIT PROCESSOR IN DIFFERENT MODES OF OPERATION
18
Patent #:
10108548
Issue Dt:
10/23/2018
Application #:
14829458
Filing Dt:
08/18/2015
Publication #:
US20160055083
Pub Dt:
02/25/2016
Title:
PROCESSORS AND METHODS FOR CACHE SPARING STORES
19
Patent #:
10318172
Issue Dt:
06/11/2019
Application #:
14873027
Filing Dt:
10/01/2015
Publication #:
US20160299700
Pub Dt:
10/13/2016
Title:
Cache Operation in a Multi-Threaded Processor
20
Patent #:
NONE
Issue Dt:
Application #:
14930740
Filing Dt:
11/03/2015
Publication #:
US20170123792
Pub Dt:
05/04/2017
Title:
Processors Supporting Endian Agnostic SIMD Instructions and Methods
21
Patent #:
10664280
Issue Dt:
05/26/2020
Application #:
14935579
Filing Dt:
11/09/2015
Publication #:
US20170132009
Pub Dt:
05/11/2017
Title:
Fetch Ahead Branch Target Buffer
22
Patent #:
10459725
Issue Dt:
10/29/2019
Application #:
15001628
Filing Dt:
01/20/2016
Publication #:
US20170206086
Pub Dt:
07/20/2017
Title:
Execution of Load Instructions in a Processor
23
Patent #:
NONE
Issue Dt:
Application #:
15079784
Filing Dt:
03/24/2016
Publication #:
US20170277539
Pub Dt:
09/28/2017
Title:
EXCEPTION HANDLING IN PROCESSOR USING BRANCH DELAY SLOT INSTRUCTION SET ARCHITECTURE
24
Patent #:
NONE
Issue Dt:
Application #:
15092728
Filing Dt:
04/07/2016
Publication #:
US20170293646
Pub Dt:
10/12/2017
Title:
APPARATUS AND METHODS FOR OUT OF ORDER ITEM SELECTION AND STATUS UPDATING
25
Patent #:
10649773
Issue Dt:
05/12/2020
Application #:
15092915
Filing Dt:
04/07/2016
Publication #:
US20170293486
Pub Dt:
10/12/2017
Title:
PROCESSORS SUPPORTING ATOMIC WRITES TO MULTIWORD MEMORY LOCATIONS & METHODS
26
Patent #:
NONE
Issue Dt:
Application #:
15093404
Filing Dt:
04/07/2016
Publication #:
US20170293556
Pub Dt:
10/12/2017
Title:
READ DISCARDS IN A PROCESSOR SYSTEM WITH WRITE-BACK CACHES
27
Patent #:
NONE
Issue Dt:
Application #:
15205445
Filing Dt:
07/08/2016
Publication #:
US20170010819
Pub Dt:
01/12/2017
Title:
CHECK POINTING A SHIFT REGISTER
28
Patent #:
10025527
Issue Dt:
07/17/2018
Application #:
15205555
Filing Dt:
07/08/2016
Publication #:
US20170010820
Pub Dt:
01/12/2017
Title:
CHECK POINTING A SHIFT REGISTER USING A CIRCULAR BUFFER
29
Patent #:
10360037
Issue Dt:
07/23/2019
Application #:
15281661
Filing Dt:
09/30/2016
Publication #:
US20170090933
Pub Dt:
03/30/2017
Title:
FETCH UNIT FOR PREDICTING TARGET FOR SUBROUTINE RETURN INSTRUCTIONS
30
Patent #:
10318296
Issue Dt:
06/11/2019
Application #:
15467073
Filing Dt:
03/23/2017
Publication #:
US20170192779
Pub Dt:
07/06/2017
Title:
SCHEDULING EXECUTION OF INSTRUCTIONS ON A PROCESSOR HAVING MULTIPLE HARDWARE THREADS WITH DIFFERENT EXECUTION RESOURCES
31
Patent #:
10754778
Issue Dt:
08/25/2020
Application #:
15488649
Filing Dt:
04/17/2017
Publication #:
US20170220471
Pub Dt:
08/03/2017
Title:
Control of Pre-Fetch Traffic
32
Patent #:
NONE
Issue Dt:
Application #:
15489975
Filing Dt:
04/18/2017
Publication #:
US20170220353
Pub Dt:
08/03/2017
Title:
STACK POINTER VALUE PREDICTION
Assignor
1
MIPS TECH LIMITED
Exec Dt:
02/16/2018
Assignee
1
MIPS TECH, LLC
3201 SCOTT BLVD.
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
VORYS, SATER, SEYMOUR AND PEASE LLP
1909 K STREET, N.W.
9TH FLOOR
WASHINGTON, DC 20006

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