|
Total properties:
10
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2009
|
Application #:
|
11276819
|
Filing Dt:
|
03/15/2006
|
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
|
Title:
|
METHOD FOR CLOCK SYNCHRONIZATION VALIDATION IN INTEGRATED CIRCUIT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2009
|
Application #:
|
11419624
|
Filing Dt:
|
05/22/2006
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
|
Title:
|
A METHOD OF OPTIMIZATION OF CLOCK GATING IN INTEGRATED CIRCUIT DESIGNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2008
|
Application #:
|
11423919
|
Filing Dt:
|
06/13/2006
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
|
Title:
|
BUS REPRESENTATION FOR EFFICIENT PHYSICAL SYNTHESIS OF INTEGRATED CIRCUIT DESIGNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
11426936
|
Filing Dt:
|
06/27/2006
|
|
Publication #:
|
|
Pub Dt:
|
01/10/2008
| | | | |
|
Title:
|
METHOD FOR RECOGNIZING AND VERIFYING FIFO STRUCTURES IN INTEGRATED CIRCUIT DESIGNS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11676232
|
Filing Dt:
|
02/16/2007
|
|
Publication #:
|
|
Pub Dt:
|
08/21/2008
| | | | |
|
Title:
|
METHOD FOR GENERATING TIMING EXCEPTIONS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11692949
|
Filing Dt:
|
03/29/2007
|
|
Publication #:
|
|
Pub Dt:
|
10/02/2008
| | | | |
|
Title:
|
METHOD FOR ACCELERATING THE GENERATION OF AN OPTIMIZED GATE-LEVEL REPRESENTATION FROM A RTL REPRESENTATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2010
|
Application #:
|
11749090
|
Filing Dt:
|
05/15/2007
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
|
Title:
|
METHOD FOR MODELING AND VERIFYING TIMING EXCEPTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
11755764
|
Filing Dt:
|
05/31/2007
|
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
|
Title:
|
METHOD FOR CHECKING CONSTRAINTS EQUIVALENCE OF AN INTEGRATED CIRCUIT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
11837174
|
Filing Dt:
|
08/10/2007
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2009
| | | | |
|
Title:
|
METHOD FOR COMPUTING POWER SAVINGS AND DETERMINING THE PREFERRED CLOCK GATING CIRCUIT OF AN INTEGRATED CIRCUIT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
11959427
|
Filing Dt:
|
12/18/2007
|
|
Publication #:
|
|
Pub Dt:
|
04/24/2008
| | | | |
|
Title:
|
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR GENERATING AND VERIFYING ISOLATION LOGIC MODULES IN DESIGN OF INTEGRATED CIRCUITS
|
|
