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Patent Assignment Details
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Reel/Frame:066368/0671   Pages: 27
Recorded: 01/19/2024
Attorney Dkt #:850063.001(OTHER LFS-4)
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 13
1
Patent #:
Issue Dt:
07/09/2013
Application #:
13564407
Filing Dt:
08/01/2012
Title:
SILICON-ON-INSULATOR CMOS INTEGRATED CIRCUIT WITH MULTIPLE THRESHOLD VOLTAGES AND A METHOD FOR DESIGNING THE SAME
2
Patent #:
Issue Dt:
10/20/2015
Application #:
13932134
Filing Dt:
07/01/2013
Publication #:
Pub Dt:
01/16/2014
Title:
ON-SOI INTEGRATED CIRCUIT COMPRISING A TRIAC FOR PROTECTION AGAINST ELECTROSTATIC DISCHARGES
3
Patent #:
Issue Dt:
05/10/2016
Application #:
13933379
Filing Dt:
07/02/2013
Publication #:
Pub Dt:
01/16/2014
Title:
On-SOI integrated circuit comprising a subjacent protection transistor
4
Patent #:
Issue Dt:
05/12/2015
Application #:
13933396
Filing Dt:
07/02/2013
Publication #:
Pub Dt:
01/16/2014
Title:
INTEGRATED CIRCUIT ON SOI COMPRISING A BIPOLAR TRANSISTOR WITH ISOLATING TRENCHES OF DISTINCT DEPTHS
5
Patent #:
Issue Dt:
07/28/2015
Application #:
14105382
Filing Dt:
12/13/2013
Publication #:
Pub Dt:
06/19/2014
Title:
METHOD FOR GENERATING A TOPOGRAPHY OF AN FDSOI INTEGRATED CIRCUIT
6
Patent #:
Issue Dt:
01/20/2015
Application #:
14134081
Filing Dt:
12/19/2013
Publication #:
Pub Dt:
06/26/2014
Title:
INTEGRATED CIRCUIT COMPRISING A CLOCK TREE CELL
7
Patent #:
Issue Dt:
04/07/2015
Application #:
14134167
Filing Dt:
12/19/2013
Publication #:
Pub Dt:
06/26/2014
Title:
INTEGRATED CIRCUIT COMPRISING A CLOCK TREE CELL
8
Patent #:
Issue Dt:
09/15/2015
Application #:
14156559
Filing Dt:
01/16/2014
Publication #:
Pub Dt:
08/21/2014
Title:
Transistor with coupled gate and ground plane
9
Patent #:
Issue Dt:
10/25/2016
Application #:
14225520
Filing Dt:
03/26/2014
Publication #:
Pub Dt:
10/02/2014
Title:
METHOD FOR CONTROLLING AN INTEGRATED CIRCUIT
10
Patent #:
Issue Dt:
07/12/2016
Application #:
14261757
Filing Dt:
04/25/2014
Publication #:
Pub Dt:
10/30/2014
Title:
INTEGRATED CIRCUIT ON SOI COMPRISING A TRANSISTOR PROTECTING FROM ELECTROSTATIC DISCHARGES
11
Patent #:
Issue Dt:
03/06/2018
Application #:
14435004
Filing Dt:
04/10/2015
Publication #:
Pub Dt:
10/08/2015
Title:
INTEGRATED CIRCUIT COMPRISING TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES
12
Patent #:
Issue Dt:
05/30/2017
Application #:
14450597
Filing Dt:
08/04/2014
Publication #:
Pub Dt:
03/05/2015
Title:
On-SOI integrated circuit equipped with a device for protecting against electrostatic discharges
13
Patent #:
Issue Dt:
08/28/2018
Application #:
15591565
Filing Dt:
05/10/2017
Publication #:
Pub Dt:
09/07/2017
Title:
SOI INTEGRATED CIRCUIT EQUIPPED WITH A DEVICE FOR PROTECTING AGAINST ELECTROSTATIC DISCHARGES
Assignor
1
Exec Dt:
01/26/2023
Assignee
1
29 BOULEVARD ROMAIN ROLLAND
MONTROUGE, FRANCE 92120
Correspondence name and address
TESSA MCCLURE
701 FIFTH AVENUE, SUITE 5400
SEED IP LAW GROUP LLP
SEATTLE, WA 98104

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