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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08794283
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02/03/1997
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Title:
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11/17/1998
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Title:
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04/25/2000
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09/29/1997
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Title:
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05/02/2000
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01/27/1998
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07/25/2000
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04/29/1998
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Title:
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10/12/1999
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05/28/1998
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12/14/1999
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12/04/2001
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08/27/1998
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11/19/2002
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05/30/2002
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01/02/2001
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11/04/1998
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Title:
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02/06/2001
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11/04/1998
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Title:
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09/04/2001
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12/23/1998
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05/09/2000
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12/29/1998
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12/30/1998
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04/20/2004
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04/25/2000
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07/30/1999
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04/10/2001
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07/30/1999
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08/22/2000
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09/10/1999
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09/25/2001
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05/14/2002
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11/18/1999
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06/26/2001
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12/28/1999
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04/02/2002
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02/18/2000
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Title:
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05/25/2004
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04/12/2000
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03/18/2003
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04/20/2000
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Title:
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05/29/2001
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04/28/2000
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Title:
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06/25/2002
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04/28/2000
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06/01/2010
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06/19/2001
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06/29/2000
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07/28/2000
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07/16/2002
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12/05/2000
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08/23/2001
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12/06/2001
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02/21/2002
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10196401
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Filing Dt:
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07/16/2002
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01/22/2004
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Title:
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CLUSTER BASED REDUNDANCY SCHEME FOR SEMICONDUCTOR MEMORIES
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05/29/2007
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10210866
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07/31/2002
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02/05/2004
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Title:
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FLASH ASSISTED ANNEALING
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07/27/2004
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10212630
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08/05/2002
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02/05/2004
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Title:
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REFRESHING MEMORY CELLS OF A PHASE CHANGE MATERIAL MEMORY DEVICE
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03/08/2011
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10215549
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08/08/2002
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02/12/2004
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Title:
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EXECUTING APPLICATIONS FROM A SEMICONDUCTOR NONVOLATILE MEMORY
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05/29/2007
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10236203
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09/06/2002
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03/11/2004
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Title:
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IN-SITU SEQUENTIAL HIGH DENSITY PLASMA DEPOSITION AND ETCH PROCESSING FOR GAP FILL
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10/30/2007
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10281857
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10/28/2002
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04/29/2004
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Title:
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ANALYZING INTERCONNECT STRUCTURES
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11/09/2004
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10290030
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11/07/2002
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06/12/2003
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Title:
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LOW POWER CHARGE PUMP CIRCUIT
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04/17/2007
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10318984
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12/13/2002
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06/17/2004
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Title:
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PHASE CHANGE MEMORY AND METHOD THEREFOR
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09/18/2007
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10319183
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12/13/2002
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06/17/2004
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Title:
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ISOLATING PHASE CHANGE MEMORY DEVICES
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11/08/2005
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10328721
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12/23/2002
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08/07/2003
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Title:
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AUTOTESTING METHOD OF A MEMORY CELL MATRIX, PARTICULARLY OF THE NON-VOLATILE TYPE
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10/26/2004
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10331116
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12/27/2002
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08/14/2003
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Title:
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REGULATION METHOD FOR THE DRAIN, BODY AND SOURCE TERMINALS VOLTAGES IN A NON-VOLATILE MEMORY CELL DURING A PROGRAM PHASE AND CORRESPONDING PROGRAM CIRCUIT
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08/08/2006
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10331161
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12/26/2002
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08/21/2003
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Title:
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PROGRAMMING METHOD FOR A MULTILEVEL MEMORY CELL
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12/07/2004
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10334126
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12/30/2002
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08/07/2003
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Title:
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POWER SUPPLY CIRCUIT STRUCTURE FOR A ROW DECODER OF A MULTILEVEL NON-VOLATILE MEMORY DEVICE
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08/01/2006
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10356351
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01/30/2003
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10/02/2003
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Title:
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02/13/2007
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10379061
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03/04/2003
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09/09/2004
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DIELECTRIC WITH SIDEWALL PASSIVATING LAYER
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08/30/2005
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10409287
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04/08/2003
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10/14/2004
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USING A TRANSVERSAL FILTER TO COMPENSATE FOR DISPERSION
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08/11/2009
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10438146
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05/13/2003
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10/30/2003
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07/19/2005
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10438175
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05/13/2003
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02/26/2004
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08/31/2004
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10447293
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05/28/2003
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04/15/2004
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04/03/2007
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10620469
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07/15/2003
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01/20/2005
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MEMORY DRIVER ARCHITECTURE AND ASSOCIATED METHODS
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01/16/2007
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10631463
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07/30/2003
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07/08/2004
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04/18/2006
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10633869
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08/04/2003
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02/10/2005
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CONTROLLING THE LOCATION OF CONDUCTION BREAKDOWN IN PHASE CHANGE MEMORIES
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02/27/2007
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10675221
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09/30/2003
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10/21/2004
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METHOD FOR ERASING NON-VOLATILE MEMORY CELLS AND CORRESPONDING MEMORY DEVICE
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09/27/2005
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10675245
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09/29/2003
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07/15/2004
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12/06/2005
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10715887
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11/18/2003
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08/05/2004
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12/19/2006
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10727341
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11/26/2003
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09/29/2005
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05/17/2005
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10728372
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12/04/2003
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08/19/2004
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10/30/2007
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10744664
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12/23/2003
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06/23/2005
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REWRITABLE FUSE MEMORY
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04/04/2006
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10746555
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12/24/2003
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09/30/2004
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04/18/2006
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12/30/2003
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10/28/2004
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11/21/2006
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10789351
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02/26/2004
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11/25/2004
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08/19/2008
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10799555
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03/10/2004
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09/15/2005
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02/05/2008
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10805168
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03/19/2004
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03/03/2005
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06/01/2010
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10805182
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03/19/2004
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11/18/2004
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04/15/2008
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06/30/2004
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01/05/2006
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01/29/2008
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10881664
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06/30/2004
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01/05/2006
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10/26/2010
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10890529
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07/12/2004
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02/24/2005
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10/24/2006
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10900666
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07/28/2004
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02/02/2006
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COMPENSATING THE WORKFUNCTION OF A METAL GATE TRANSISTOR FOR ABSTRACTION BY THE GATE DIELECTRIC LAYER
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05/08/2007
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10909749
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08/02/2004
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02/03/2005
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METHOD FOR THE FABRICATION OF ISOLATION STRUCTURES
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