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Total properties:
40
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09606135
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Filing Dt:
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06/28/2000
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Title:
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METHOD AND APPARATUS FOR PROCESS CONTROL OF ALIGNMENT IN DUAL DAMASCENE PROCESSES
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09614312
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Filing Dt:
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07/12/2000
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Title:
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METHOD AND APPARATUS FOR REDUCING DEPOSITION VARIATION BY MODELING POST-CLEAN CHAMBER PERFORMANCE
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Patent #:
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Issue Dt:
|
12/09/2003
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Application #:
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09640080
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Filing Dt:
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08/17/2000
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Title:
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REVERSE MASK AND OXIDE LAYER DEPOSITION FOR REDUCTION OF VERTICAL CAPACITANCE VARIATION IN MULTI-LAYER METALLIZATION SYSTEMS
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Patent #:
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Issue Dt:
|
02/25/2003
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Application #:
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09650545
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Filing Dt:
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08/30/2000
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Title:
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METHOD OF CONTROLLING PHOTORESIST THICKNESS BASED UPON PHOTORESIST VISCOSITY
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Patent #:
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Issue Dt:
|
08/27/2002
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Application #:
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09651760
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Filing Dt:
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08/30/2000
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Title:
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METHOD OF COPPER-POLYSILICON GATE FORMATION
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Patent #:
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Issue Dt:
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03/19/2002
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Application #:
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09655699
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Filing Dt:
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09/06/2000
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Title:
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Forming and filling a recess in interconnect with alloy to minimize electromigration
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Patent #:
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Issue Dt:
|
05/14/2002
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Application #:
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09664950
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Filing Dt:
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09/19/2000
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Title:
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BC13/AR CHEMISTRY FOR METAL OVERETCHING ON A HIGH DENSITY PLASMA ETCHER
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Patent #:
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Issue Dt:
|
06/11/2002
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Application #:
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09678504
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Filing Dt:
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10/02/2000
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Title:
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PLATING SYSTEM WITH SHIELDED SECONDARY ANODE FOR SEMICONDUCTOR MANUFACTURING
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Patent #:
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Issue Dt:
|
10/08/2002
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Application #:
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09772750
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Filing Dt:
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01/29/2001
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Title:
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COHERENT ALLOY DIFFUSION BARRIER FOR INTEGRATED CIRCUIT INTERCONNECTS
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Patent #:
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Issue Dt:
|
05/27/2003
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Application #:
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09776087
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Filing Dt:
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02/02/2001
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Title:
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AUTOMATED METHOD OF CONTROLLING PHOTORESIST DEVELOP TIME TO CONTROL CRITICAL DIMENSIONS, AND SYSTEM FOR ACCOMPLISHING SAME
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Patent #:
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Issue Dt:
|
04/02/2002
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Application #:
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09780531
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Filing Dt:
|
02/21/2001
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Title:
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METHOD OF MAKING A SLOT VIA FILLED DUAL DAMASCENE STRUCTURE WITH MIDDLE STOP LAYER
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Patent #:
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Issue Dt:
|
10/02/2001
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Application #:
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09781389
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Filing Dt:
|
02/12/2001
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Title:
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Formation of confined halo regions in field effect transistor
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Patent #:
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|
Issue Dt:
|
09/03/2002
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Application #:
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09788472
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Filing Dt:
|
02/21/2001
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|
Title:
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METHOD OF MAKING A SLOT VIA FILLED DUAL DAMASCENE STRUCTURE WITH A MIDDLE STOP LAYER
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|
|
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Patent #:
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|
Issue Dt:
|
05/21/2002
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Application #:
|
09788641
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Filing Dt:
|
02/21/2001
|
|
Title:
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METHOD OF MAKING A SLOT VIA FILLED DUAL DAMASCENE STRUCTURE WITH MIDDLE STOP LAYER
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|
|
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Patent #:
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|
Issue Dt:
|
03/11/2003
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Application #:
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09825750
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Filing Dt:
|
04/03/2001
|
|
Title:
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METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A METAL OXIDE HIGH-K GATE INSULATOR BY LOCALIZED LASER IRRADIATION AND A DEVICE THEREBY FORMED
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|
|
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Patent #:
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|
Issue Dt:
|
09/09/2003
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Application #:
|
09827534
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Filing Dt:
|
04/06/2001
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|
Title:
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METHOD OF IDENTIFYING FILM STACKS BASED UPON OPTICAL PROPERTIES
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|
|
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Patent #:
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|
Issue Dt:
|
10/08/2002
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Application #:
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09876259
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Filing Dt:
|
06/06/2001
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|
Title:
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SEMICONDUCTOR WAFER POLISHING APPARATUS
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Patent #:
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Issue Dt:
|
10/18/2005
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Application #:
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09883883
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Filing Dt:
|
06/18/2001
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|
Title:
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CLOSED LOOP RESIDUAL GAS ANALYZER PROCESS CONTROL TECHNIQUE
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Patent #:
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Issue Dt:
|
02/10/2004
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Application #:
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09884182
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Filing Dt:
|
06/19/2001
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|
Title:
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PROCESS FOR FORMING A PHOTORESIST MASK
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Patent #:
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|
Issue Dt:
|
09/24/2002
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Application #:
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09894525
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Filing Dt:
|
06/27/2001
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|
Title:
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INTEGRATED CIRCUIT MANUFACTURING METHOD INCLUDING SEED LAYER DEPOSITION, REMOVAL, AND SUBSEQUENT DEPOSITION
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Patent #:
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Issue Dt:
|
02/10/2004
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Application #:
|
09924670
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Filing Dt:
|
08/07/2001
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|
Title:
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MULTILAYER ANTI-REFLECTIVE COATING FOR SEMICONDUCTOR LITHOGRAPHY
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|
|
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Patent #:
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|
Issue Dt:
|
04/22/2003
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Application #:
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10207494
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Filing Dt:
|
07/29/2002
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|
Publication #:
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Pub Dt:
|
12/12/2002
| | | | |
|
Title:
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METHOD AND APPARATUS FOR CONTROLLING A STEPPER
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Patent #:
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Issue Dt:
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05/29/2007
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Application #:
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11082122
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Filing Dt:
|
03/16/2005
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Publication #:
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|
Pub Dt:
|
01/05/2006
| | | | |
|
Title:
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METHOD OF FORMING AN EPITAXIAL LAYER FOR RAISED DRAIN AND SOURCE REGIONS BY REMOVING SURFACE DEFECTS OF THE INITIAL CRYSTAL SURFACE
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Patent #:
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|
Issue Dt:
|
02/19/2008
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Application #:
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11145327
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Filing Dt:
|
06/03/2005
|
|
Title:
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OPTIMIZING CRITICAL DIMENSION UNIFORMITY UTILIZING A RESIST BAKE PLATE SIMULATOR
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Patent #:
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|
Issue Dt:
|
01/08/2008
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Application #:
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11177216
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Filing Dt:
|
07/08/2005
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|
Publication #:
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Pub Dt:
|
06/01/2006
| | | | |
|
Title:
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METHOD OF FORMING SIDEWALL SPACERS
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Patent #:
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|
Issue Dt:
|
10/02/2007
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Application #:
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11180393
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Filing Dt:
|
07/13/2005
|
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Title:
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METHOD AND APPARATUS FOR CLASSIFYING FAULTS BASED ON WAFER STATE DATA AND SENSOR TOOL TRACE DATA
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Patent #:
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Issue Dt:
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03/10/2009
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Application #:
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11221078
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Filing Dt:
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09/07/2005
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Title:
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METHOD AND APPARATUS FOR DYNAMIC ADJUSTMENT OF SENSOR AND/OR METROLOGY SENSITIVITIES
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Patent #:
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Issue Dt:
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10/09/2007
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Application #:
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11280484
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Filing Dt:
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11/16/2005
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Publication #:
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Pub Dt:
|
10/05/2006
| | | | |
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Title:
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TECHNIQUE FOR FORMING A TRANSISTOR HAVING RAISED DRAIN AND SOURCE REGIONS WITH A TRI-LAYER HARD MASK FOR GATE PATTERNING
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Patent #:
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Issue Dt:
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09/29/2009
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Application #:
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11467216
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Filing Dt:
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08/25/2006
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Publication #:
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Pub Dt:
|
05/31/2007
| | | | |
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Title:
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A SEMICONDUCTOR DEVICE COMPRISING A COPPER ALLOY AS A BARRIER LAYER IN A COPPER METALLIZATION LAYER
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Patent #:
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Issue Dt:
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10/26/2010
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Application #:
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11468834
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Filing Dt:
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08/31/2006
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Publication #:
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Pub Dt:
|
05/31/2007
| | | | |
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Title:
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METHOD FOR REMOVING A PASSIVATION LAYER PRIOR TO DEPOSITING A BARRIER LAYER IN A COPPER METALLIZATION LAYER
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Patent #:
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Issue Dt:
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11/03/2009
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Application #:
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11753438
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Filing Dt:
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05/24/2007
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Publication #:
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Pub Dt:
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11/27/2008
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Title:
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GATE STRAINING IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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11/15/2011
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Application #:
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11777355
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Filing Dt:
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07/13/2007
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Publication #:
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Pub Dt:
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07/03/2008
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Title:
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METHOD OF TESTING AN INTEGRITY OF A MATERIAL LAYER IN A SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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10/06/2009
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Application #:
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11861534
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Filing Dt:
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09/26/2007
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Publication #:
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Pub Dt:
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03/26/2009
| | | | |
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Title:
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METHOD OF FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES USING HALO IMPLANT SHADOWING
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Patent #:
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Issue Dt:
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11/22/2011
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Application #:
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11867972
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Filing Dt:
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10/05/2007
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Publication #:
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Pub Dt:
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08/28/2008
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Title:
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HIGH YIELD PLASMA ETCH PROCESS FOR INTERLAYER DIELECTRICS
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Patent #:
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Issue Dt:
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07/19/2011
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Application #:
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12045907
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Filing Dt:
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03/11/2008
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Publication #:
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Pub Dt:
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03/05/2009
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Title:
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METHOD OF FORMING A METAL DIRECTLY ON A CONDUCTIVE BARRIER LAYER BY ELECTROCHEMICAL DEPOSITION USING AN OXYGEN-DEPLETED AMBIENT
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Patent #:
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Issue Dt:
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02/28/2012
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Application #:
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12122075
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Filing Dt:
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05/16/2008
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Publication #:
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Pub Dt:
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04/02/2009
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Title:
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METHOD AND SYSTEM FOR CONTROLLING TRANSPORT SEQUENCING IN A PROCESS TOOL BY A LOOK-AHEAD MODE
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Patent #:
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Issue Dt:
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05/29/2012
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Application #:
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12472969
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Filing Dt:
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05/27/2009
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Publication #:
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Pub Dt:
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02/04/2010
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Title:
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DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS BY LOCAL GATE ENGINEERING
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Patent #:
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Issue Dt:
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01/17/2012
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Application #:
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12565323
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Filing Dt:
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09/23/2009
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Publication #:
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Pub Dt:
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05/06/2010
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Title:
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REDUCING METAL VOIDS IN A METALLIZATION LAYER STACK OF A SEMICONDUCTOR DEVICE BY PROVIDING A DIELECTRIC BARRIER LAYER
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Patent #:
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Issue Dt:
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01/25/2011
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Application #:
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12841313
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Filing Dt:
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07/22/2010
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Publication #:
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Pub Dt:
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11/11/2010
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Title:
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TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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13158773
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Filing Dt:
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06/13/2011
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Publication #:
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Pub Dt:
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10/20/2011
| | | | |
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Title:
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SIDEWALL GRAPHENE DEVICES FOR 3-D ELECTRONICS
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