Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Reel/Frame: | 010630/0685 | |
| Pages: | 2 |
| | Recorded: | 08/26/1999 | | |
Conveyance: | (ASSIGNMENT OF ASSIGNOR'S INTEREST) R-RECORD TO CORRECT THE RECORDATION DATE, 08/14/99 TO 08/26/99 PREVIOUSLY RECORDED AT REEL 10194 FRAME 0827. |
|
Total properties:
1
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2002
|
Application #:
|
09336666
|
Filing Dt:
|
06/18/1999
|
Title:
|
METHOD AND CIRCUIT FOR MINIMIZING THE CHARGING EFFECT DURING MANUFACTURE OF SEMICONDUCTOR DEVICES
|
|
Assignee
|
|
|
SOUTH INDUSTRIAL AREA |
BEIT TOPPER, 65 HAMELACHA STREET |
NETANYA 42504, ISRAEL |
|
Correspondence name and address
|
|
DARBY & DARBY P.C.
|
|
JOSEPH B. LERCH
|
|
805 THIRD AVENUE, 27TH FLOOR
|
|
NEW YORK, NEW YORK 10022-7513
|
Search Results as of:
06/18/2024 08:35 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|