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Patent Assignment Details

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Reel/Frame:	023796/0685			Pages:	6
		Recorded:	01/14/2010
Attorney Dkt #:	TIPI 5.2-004
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 16

Patent #:	5818107	Issue Dt:	10/06/1998	Application #:	08785187	Filing Dt:	01/17/1997
Title:	CHIP STACKING BY EDGE METALLIZATION

Patent #:	6195883	Issue Dt:	03/06/2001	Application #:	09047984	Filing Dt:	03/25/1998
Title:	FULL ADDITIVE PROCESS WITH FILLED PLATED THROUGH HOLES

Patent #:	6497943	Issue Dt:	12/24/2002	Application #:	09503395	Filing Dt:	02/14/2000
Title:	SURFACE METAL BALANCING TO REDUCE CHIP CARRIER FLEXING

Patent #:	6538213	Issue Dt:	03/25/2003	Application #:	09506951	Filing Dt:	02/18/2000
Title:	HIGH DENSITY DESIGN FOR ORGANIC CHIP CARRIERS

Patent #:	6414386	Issue Dt:	07/02/2002	Application #:	09531971	Filing Dt:	03/20/2000
Title:	METHOD TO REDUCE NUMBER OF WIRE-BOND LOOP HEIGHTS VERSUS THE TOTAL QUANTITY OF POWER AND SIGNAL RINGS

Patent #:	6931723	Issue Dt:	08/23/2005	Application #:	09665366	Filing Dt:	09/19/2000
Title:	ORGANIC DIELECTRIC ELECTRONIC INTERCONNECT STRUCTURES AND METHOD FOR MAKING

Patent #:	6528179	Issue Dt:	03/04/2003	Application #:	09691935	Filing Dt:	10/19/2000
Title:	REDUCTION OF CHIP CARRIER FLEXING DURING THERMAL CYCLING

Patent #:	6664485	Issue Dt:	12/16/2003	Application #:	09778702	Filing Dt:	02/07/2001
Publication #:	US20010007289	Pub Dt:	07/12/2001
Title:	FULL ADDITIVE PROCESS WITH FILLED PLATED THROUGH HOLES

Patent #:	6418616	Issue Dt:	07/16/2002	Application #:	09795852	Filing Dt:	02/28/2001
Publication #:	US20010009066	Pub Dt:	07/26/2001
Title:	FULL ADDITIVE PROCESS WITH FILLED PLATED THROUGH HOLES

Patent #:	6717255	Issue Dt:	04/06/2004	Application #:	10032675	Filing Dt:	10/23/2001
Publication #:	US20020055277	Pub Dt:	05/09/2002
Title:	CHIP CARRIER FOR A HIGH-FREQUENCY ELECTRONIC PACKAGE

Patent #:	6747331	Issue Dt:	06/08/2004	Application #:	10197335	Filing Dt:	07/17/2002
Publication #:	US20040012086	Pub Dt:	01/22/2004
Title:	METHOD AND PACKAGING STRUCTURE FOR OPTIMIZING WARPAGE OF FLIP CHIP ORGANIC PACKAGES

Patent #:	7084509	Issue Dt:	08/01/2006	Application #:	10263909	Filing Dt:	10/03/2002
Publication #:	US20040065960	Pub Dt:	04/08/2004
Title:	ELECTRONIC PACKAGE WITH FILLED BLINDS VIAS

Patent #:	6924224	Issue Dt:	08/02/2005	Application #:	10729174	Filing Dt:	12/05/2003
Publication #:	US20040132279	Pub Dt:	07/08/2004
Title:	METHOD OF FORMING FILLED BLIND VIAS

Patent #:	7026706	Issue Dt:	04/11/2006	Application #:	10771728	Filing Dt:	02/04/2004
Publication #:	US20040155339	Pub Dt:	08/12/2004
Title:	METHOD AND PACKAGING STRUCTURE FOR OPTIMIZING WARPAGE OF FLIP CHIP ORGANIC PACKAGES

Patent #:	6946746	Issue Dt:	09/20/2005	Application #:	10801764	Filing Dt:	03/16/2004
Publication #:	US20040173893	Pub Dt:	09/09/2004
Title:	METHOD TO REDUCE NUMBER OF WIRE-BOND LOOP HEIGHTS VERSUS THE TOTAL QUANTITY OF POWER AND SIGNAL RINGS

Patent #:	7253512	Issue Dt:	08/07/2007	Application #:	11074848	Filing Dt:	03/09/2005
Publication #:	US20050150686	Pub Dt:	07/14/2005
Title:	ORGANIC DIELECTRIC ELECTRONIC INTERCONNECT STRUCTURES AND METHOD FOR MAKING

Assignor

Exec Dt:

09/30/2009

Assignee

3025 ORCHARD PARKWAY

SAN JOSE, CALIFORNIA 95134

Correspondence name and address
	DARYL K. NEFF
	LERNER, DAVID, LITTENBERG, KRUMHOLZ &
	MENTLIK, LLP
	600 SOUTH AVENUE WEST
	WESTFIELD, NJ 07090

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