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Reel/Frame:027698/0690   Pages: 12
Recorded: 02/13/2012
Attorney Dkt #:TIPI 5.2-029
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 38
1
Patent #:
5615169
Issue Dt:
03/25/1997
Application #:
08522032
Filing Dt:
08/31/1995
Title:
METHOD AND STRUCTURE FOR CONTROLLING INTERNAL OPERATIONS OF A DRAM ARRAY
2
Patent #:
5729152
Issue Dt:
03/17/1998
Application #:
08549610
Filing Dt:
10/27/1995
Title:
TERMINATION CIRCUITS FOR REDUCED SWING SIGNAL LINES AND METHODS FOR OPERATING SAME
3
Patent #:
5703827
Issue Dt:
12/30/1997
Application #:
08610108
Filing Dt:
02/29/1996
Title:
METHOD AND STRUCTURE FOR GENERATING A BOOSTED WORD LINE VOLTAGE AND BACK BIAS VOLTAGE FOR A MEMORY ARRAY
4
Patent #:
5784705
Issue Dt:
07/21/1998
Application #:
08679873
Filing Dt:
07/15/1996
Title:
METHOD AND STRUCTURE FOR PERFORMING PIPELINE BURST ACCESSES IN A SEMICONDUCTOR MEMORY
5
Patent #:
5940851
Issue Dt:
08/17/1999
Application #:
08757494
Filing Dt:
11/27/1996
Title:
METHOD AND APPARATUS FOR DRAM REFRESH USING MASTER, SLAVE AND SELF- REFRESH MODES
6
Patent #:
5708624
Issue Dt:
01/13/1998
Application #:
08757866
Filing Dt:
11/27/1996
Title:
METHOD AND STRUCTURE FOR CONTROLLING INTERNAL OPERATIONS OF A DRAM ARRAY
7
Patent #:
5829026
Issue Dt:
10/27/1998
Application #:
08812000
Filing Dt:
03/05/1997
Title:
METHOD AND STRUCTURE FOR IMPLEMENTING A CACHE MEMORY USING A DRAM ARRAY
8
Patent #:
5805509
Issue Dt:
09/08/1998
Application #:
08891124
Filing Dt:
07/10/1997
Title:
METHOD AND STRUCTURE FOR GENERATING A BOOSTED WORD LINE VOLTAGE AND BACK BIAS VOLTAFE FOR A MEMORY ARRAY
9
Patent #:
6128700
Issue Dt:
10/03/2000
Application #:
08942254
Filing Dt:
10/01/1997
Title:
SYSTEM UTILIZING A DRAM ARRAY AS A NEXT LEVEL CACHE MEMORY AND METHOD FOR OPERATING SAME
10
Patent #:
6028804
Issue Dt:
02/22/2000
Application #:
09037396
Filing Dt:
03/09/1998
Title:
METHOD AND APPARATUS FOR 1-T SCRAM COMPATIBLE MEMORY
11
Patent #:
6295593
Issue Dt:
09/25/2001
Application #:
09153099
Filing Dt:
09/14/1998
Title:
METHOD AND STRUCTURE FOR UTILIZING A DRAM ARRAY AS SECOND LEVEL CACHE MEMORY
12
Patent #:
6222785
Issue Dt:
04/24/2001
Application #:
09234778
Filing Dt:
01/20/1999
Title:
METHOD AND APPARATUS FOR REFRESHING A SEMICONDUCTOR MEMORY USING IDLE MEMORY CYCLES
13
Patent #:
6147914
Issue Dt:
11/14/2000
Application #:
09332757
Filing Dt:
06/14/1999
Title:
ON-CHIP WORD LINE VOLTAGE GENERATION FOR DRAM EMBEDDED IN LOGIC PROCESS
14
Patent #:
6393504
Issue Dt:
05/21/2002
Application #:
09493781
Filing Dt:
01/28/2000
Title:
DYNAMIC ADDRESS MAPPING AND REDUNDANCY IN A MODULAR MEMORY DEVICE
15
Patent #:
6754746
Issue Dt:
06/22/2004
Application #:
09535656
Filing Dt:
03/23/2000
Title:
MEMORY ARRAY WITH READ/WRITE METHODS
16
Patent #:
6370073
Issue Dt:
04/09/2002
Application #:
09768908
Filing Dt:
01/23/2001
Publication #:
US20010007538
Pub Dt:
07/12/2001
Title:
Single-Port multi-bank memory system having read and write buffers and method of operating same
17
Patent #:
6468855
Issue Dt:
10/22/2002
Application #:
09772434
Filing Dt:
01/29/2001
Publication #:
US20010052610
Pub Dt:
12/20/2001
Title:
REDUCED TOPOGRAPHY DRAM CELL FABRICATED USING A MODIFIED LOGIC PROCESS AND METHOD FOR OPERATING SAME
18
Patent #:
6504780
Issue Dt:
01/07/2003
Application #:
09846093
Filing Dt:
04/30/2001
Publication #:
US20010026493
Pub Dt:
10/04/2001
Title:
METHOD AND APPARATUS FOR COMPLETELY HIDING REFRESH OPERATIONS IN A DRAM DEVICE USING CLOCK DIVISION
19
Patent #:
6510492
Issue Dt:
01/21/2003
Application #:
09851713
Filing Dt:
05/08/2001
Publication #:
US20010037428
Pub Dt:
11/01/2001
Title:
APPARATUS FOR CONTROLLING DATA TRANSFER BETWEEN A BUS AND MEMORY ARRAY AND METHOD FOR OPERATING SAME
20
Patent #:
6808169
Issue Dt:
10/26/2004
Application #:
09948163
Filing Dt:
09/06/2001
Publication #:
US20020008271
Pub Dt:
01/24/2002
Title:
NON-VOLATILE MEMORY SYSTEM
21
Patent #:
6449685
Issue Dt:
09/10/2002
Application #:
10007334
Filing Dt:
10/29/2001
Publication #:
US20020056022
Pub Dt:
05/09/2002
Title:
READ/WRITE BUFFERS FOR COMPLETE HIDING OF THE REFRESH OF A SEMICONDUCTOR MEMORY AND METHOD OF OPERATING SAME
22
Patent #:
6654295
Issue Dt:
11/25/2003
Application #:
10043386
Filing Dt:
01/11/2002
Publication #:
US20020053691
Pub Dt:
05/09/2002
Title:
REDUCED TOPOGRAPHY DRAM CELL FABRICATED USING A MODIFIED LOGIC PROCESS AND METHOD FOR OPERATING SAME
23
Patent #:
6549483
Issue Dt:
04/15/2003
Application #:
10109878
Filing Dt:
04/01/2002
Publication #:
US20020176311
Pub Dt:
11/28/2002
Title:
RAM HAVING DYNAMICALLY SWITCHABLE ACCESS MODES
24
Patent #:
6707743
Issue Dt:
03/16/2004
Application #:
10114282
Filing Dt:
04/03/2002
Publication #:
US20020105844
Pub Dt:
08/08/2002
Title:
METHOD AND APPARATUS FOR COMPLETELY HIDING REFRESH OPERATIONS IN A DRAM DEVICE USING MULTIPLE CLOCK DIVISION
25
Patent #:
6751157
Issue Dt:
06/15/2004
Application #:
10279363
Filing Dt:
10/23/2002
Publication #:
US20030039163
Pub Dt:
02/27/2003
Title:
METHOD AND APPARATUS FOR COMPLETELY HIDING REFRESH OPERATIONS IN A DRAM DEVICE USING CLOCK DIVISION
26
Patent #:
6898140
Issue Dt:
05/24/2005
Application #:
10300427
Filing Dt:
11/20/2002
Publication #:
US20030067830
Pub Dt:
04/10/2003
Title:
METHOD AND APPARATUS FOR TEMPERATURE ADAPTIVE REFRESH IN 1T-SRAM COMPATIBLE MEMORY USING THE SUBTHRESHOLD CHARACTERISTICS OF MOSFET TRANSISTORS
27
Patent #:
6894941
Issue Dt:
05/17/2005
Application #:
10308157
Filing Dt:
12/03/2002
Publication #:
US20030086316
Pub Dt:
05/08/2003
Title:
RAM HAVING DYNAMICALLY SWITCHABLE ACCESS MODES
28
Patent #:
6744676
Issue Dt:
06/01/2004
Application #:
10374956
Filing Dt:
02/25/2003
Publication #:
US20030151072
Pub Dt:
08/14/2003
Title:
DRAM CELL HAVING A CAPACITOR STRUCTURE FABRICATED PARTIALLY IN A CAVITY AND METHOD FOR OPERATING SAME
29
Patent #:
6795364
Issue Dt:
09/21/2004
Application #:
10377677
Filing Dt:
02/28/2003
Publication #:
US20040170079
Pub Dt:
09/02/2004
Title:
METHOD AND APPARATUS FOR LENGTHENING THE DATA-RETENTION TIME OF A DRAM DEVICE IN STANDBY MODE
30
Patent #:
7206913
Issue Dt:
04/17/2007
Application #:
10927157
Filing Dt:
08/25/2004
Publication #:
US20050027929
Pub Dt:
02/03/2005
Title:
HIGH SPEED MEMORY SYSTEM
31
Patent #:
7392456
Issue Dt:
06/24/2008
Application #:
10997604
Filing Dt:
11/23/2004
Publication #:
US20060123322
Pub Dt:
06/08/2006
Title:
PREDICTIVE ERROR CORRECTION CODE GENERATION FACILITATING HIGH-SPEED BYTE-WRITE IN A SEMICONDUCTOR MEMORY
32
Patent #:
7274618
Issue Dt:
09/25/2007
Application #:
11166856
Filing Dt:
06/24/2005
Publication #:
US20060291321
Pub Dt:
12/28/2006
Title:
WORD LINE DRIVER FOR DRAM EMBEDDED IN A LOGIC PROCESS
33
Patent #:
7275200
Issue Dt:
09/25/2007
Application #:
11221098
Filing Dt:
09/06/2005
Publication #:
US20060112321
Pub Dt:
05/25/2006
Title:
TRANSPARENT ERROR CORRECTING MEMORY THAT SUPPORTS PARTIAL-WORD WRITE
34
Patent #:
7671401
Issue Dt:
03/02/2010
Application #:
11262141
Filing Dt:
10/28/2005
Publication #:
US20070097743
Pub Dt:
05/03/2007
Title:
NON-VOLATILE MEMORY IN CMOS LOGIC PROCESS
35
Patent #:
7522456
Issue Dt:
04/21/2009
Application #:
12021264
Filing Dt:
01/28/2008
Publication #:
US20080137410
Pub Dt:
06/12/2008
Title:
NON-VOLATILE MEMORY EMBEDDED IN A CONVENTIONAL LOGIC PROCESS AND METHODS FOR OPERATING SAME
36
Patent #:
7633810
Issue Dt:
12/15/2009
Application #:
12021280
Filing Dt:
01/28/2008
Publication #:
US20080137438
Pub Dt:
06/12/2008
Title:
NON-VOLATILE MEMORY EMBEDDED IN A CONVENTIONAL LOGIC PROCESS AND METHODS FOR OPERATING SAME
37
Patent #:
7633811
Issue Dt:
12/15/2009
Application #:
12021286
Filing Dt:
01/28/2008
Publication #:
US20080186778
Pub Dt:
08/07/2008
Title:
NON-VOLATILE MEMORY EMBEDDED IN A CONVENTIONAL LOGIC PROCESS AND METHODS FOR OPERATING SAME
38
Patent #:
7684229
Issue Dt:
03/23/2010
Application #:
12048176
Filing Dt:
03/13/2008
Publication #:
US20080158929
Pub Dt:
07/03/2008
Title:
SCALABLE EMBEDDED DRAM ARRAY
Assignor
1
MOSYS, INC.
Exec Dt:
01/30/2012
Assignee
1
INVENSAS CORPORATION
2702 ORCHARD PARKWAY
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
DARYL K, NEFF
LERNER, DAVID, LITTENBERG, KRUMHOLZ &
MENTLIK, LLP
600 SOUTH AVENUE WEST
WESTFIELD, NJ 07090

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