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Reel/Frame:031615/0690   Pages: 4
Recorded: 11/15/2013
Attorney Dkt #:0403-02781
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
03/24/2015
Application #:
14081806
Filing Dt:
11/15/2013
Publication #:
Pub Dt:
03/13/2014
Title:
MEMORY INTERFACE CIRCUITS INCLUDING CALIBRATION FOR CAS LATENCY COMPENSATION IN A PLURALITY OF BYTE LANES
Assignors
1
Exec Dt:
11/14/2013
2
Exec Dt:
11/14/2013
Assignee
1
3375 SCOTT BOULEVARD
#206
SANTA CLARA, CALIFORNIA 95054
Correspondence name and address
MICHAEL J. CHERSKOV
123 WEST MADISON STREET
SUITE 400
CHICAGO, IL 60602

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