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Reel/Frame:047202/0690   Pages: 9
Recorded: 10/06/2018
Attorney Dkt #:CAVIUM LLC PORTFOLIO
Conveyance: CONVERSION
Total properties: 37
1
Patent #:
Issue Dt:
10/03/2017
Application #:
12774608
Filing Dt:
05/05/2010
Publication #:
Pub Dt:
11/10/2011
Title:
SYSTEM AND METHOD FOR LOW-LATENCY MULTIMEDIA STREAMING
2
Patent #:
Issue Dt:
03/01/2016
Application #:
14145374
Filing Dt:
12/31/2013
Publication #:
Pub Dt:
07/02/2015
Title:
METHOD AND SYSTEM FOR SKIPPING OVER GROUP(S) OF RULES BASED ON SKIP GROUP RULE
3
Patent #:
Issue Dt:
01/10/2017
Application #:
14145918
Filing Dt:
12/31/2013
Publication #:
Pub Dt:
07/02/2015
Title:
MULTI-RULE APPROACH TO ENCODING A GROUP OF RULES
4
Patent #:
Issue Dt:
02/23/2016
Application #:
14150550
Filing Dt:
01/08/2014
Publication #:
Pub Dt:
07/09/2015
Title:
PROCESSING REQUEST KEYS BASED ON A KEY SIZE SUPPORTED BY UNDERLYING PROCESSING ELEMENTS
5
Patent #:
Issue Dt:
08/30/2016
Application #:
14150572
Filing Dt:
01/08/2014
Publication #:
Pub Dt:
07/09/2015
Title:
METHOD AND APPARATUS FOR COMPILING SEARCH TREES FOR PROCESSING REQUEST KEYS BASED ON A KEY SIZE SUPPORTED BY UNDERLYING PROCESSING ELEMENTS
6
Patent #:
NONE
Issue Dt:
Application #:
14150602
Filing Dt:
01/08/2014
Publication #:
Pub Dt:
07/09/2015
Title:
METHODS AND SYSTEMS FOR SINGLE INSTRUCTION MULTIPLE DATA PROGRAMMABLE PACKET PARSERS
7
Patent #:
Issue Dt:
10/15/2019
Application #:
14150622
Filing Dt:
01/08/2014
Publication #:
Pub Dt:
07/09/2015
Title:
PACKET PARSING ENGINE
8
Patent #:
Issue Dt:
05/30/2017
Application #:
14150761
Filing Dt:
01/08/2014
Publication #:
Pub Dt:
07/09/2015
Title:
CONDITION CODE APPROACH FOR COMPARING RULE AND PACKET DATA THAT ARE PROVIDED IN PORTIONS
9
Patent #:
Issue Dt:
05/09/2017
Application #:
14152817
Filing Dt:
01/10/2014
Publication #:
Pub Dt:
07/16/2015
Title:
BLOCK MASK REGISTER KEY PROCESSING BY COMPILING DATA STRUCTURES TO TRAVERSE RULES AND CREATING A NEW RULE SET
10
Patent #:
NONE
Issue Dt:
Application #:
14170955
Filing Dt:
02/03/2014
Publication #:
Pub Dt:
08/06/2015
Title:
METHOD AND AN APPARATUS FOR WORK PACKET QUEUING, SCHEDULING, AND ORDERING WITH CONFLICT QUEUING
11
Patent #:
Issue Dt:
05/14/2019
Application #:
14542298
Filing Dt:
11/14/2014
Publication #:
Pub Dt:
05/19/2016
Title:
METHOD AND APPARATUS FOR PERFORMING A WEIGHTED QUEUE SCHEDULING USING A SET OF FAIRNESS FACTORS
12
Patent #:
Issue Dt:
10/23/2018
Application #:
14542350
Filing Dt:
11/14/2014
Publication #:
Pub Dt:
05/19/2016
Title:
PACKET SCHEDULING USING HIERARCHICAL SCHEDULING PROCESS
13
Patent #:
Issue Dt:
10/15/2019
Application #:
14542393
Filing Dt:
11/14/2014
Publication #:
Pub Dt:
05/19/2016
Title:
PACKET SCHEDULING USING HIERARCHICAL SCHEDULING PROCESS WITH PRIORITY PROPAGATION
14
Patent #:
Issue Dt:
03/21/2017
Application #:
14634446
Filing Dt:
02/27/2015
Publication #:
Pub Dt:
08/04/2016
Title:
AUTOMATED FLIP-FLOP INSERTIONS IN PHYSICAL DESIGN WITHOUT PERTURBATION OF ROUTING
15
Patent #:
Issue Dt:
03/21/2017
Application #:
14664680
Filing Dt:
03/20/2015
Publication #:
Pub Dt:
09/22/2016
Title:
REPEATER INSERTIONS PROVIDING REDUCED ROUTING PERTURBATION CAUSED BY FLIP-FLOP INSERTIONS
16
Patent #:
Issue Dt:
02/18/2020
Application #:
14671900
Filing Dt:
03/27/2015
Publication #:
Pub Dt:
09/29/2016
Title:
METHOD AND APPARATUS FOR BYPASS ROUTING OF MULTICAST DATA PACKETS AND AVOIDING REPLICATION TO REDUCE OVERALL SWITCH LATENCY
17
Patent #:
Issue Dt:
01/17/2017
Application #:
14675307
Filing Dt:
03/31/2015
Publication #:
Pub Dt:
10/06/2016
Title:
IDENTIFYING INVERSION ERROR IN LOGIC EQUIVALENCE CHECK
18
Patent #:
Issue Dt:
05/28/2019
Application #:
14675342
Filing Dt:
03/31/2015
Publication #:
Pub Dt:
10/06/2016
Title:
APPROACH FOR CHIP-LEVEL FLOP INSERTION AND VERIFICATION BASED ON LOGIC INTERFACE DEFINITION
19
Patent #:
Issue Dt:
10/17/2017
Application #:
14675356
Filing Dt:
03/31/2015
Publication #:
Pub Dt:
03/09/2017
Title:
DETERMINATION OF FLIP-FLOP COUNT IN PHYSICAL DESIGN
20
Patent #:
Issue Dt:
11/03/2020
Application #:
14675403
Filing Dt:
03/31/2015
Publication #:
Pub Dt:
10/06/2016
Title:
APPROACH FOR LOGIC SIGNAL GROUPING AND RTL GENERATION USING XML
21
Patent #:
Issue Dt:
11/19/2019
Application #:
14675450
Filing Dt:
03/31/2015
Publication #:
Pub Dt:
10/06/2016
Title:
METHOD AND APPARATUS FOR USING MULTIPLE LINKED MEMORY LISTS
22
Patent #:
Issue Dt:
11/17/2020
Application #:
14940538
Filing Dt:
11/13/2015
Publication #:
Pub Dt:
05/19/2016
Title:
CARRY CHAIN FOR SIMD OPERATIONS
23
Patent #:
Issue Dt:
10/20/2020
Application #:
14940585
Filing Dt:
11/13/2015
Publication #:
Pub Dt:
05/19/2016
Title:
IMPLEMENTING 128-BIT SIMD OPERATIONS ON A 64-BIT DATAPATH
24
Patent #:
Issue Dt:
07/11/2017
Application #:
14940679
Filing Dt:
11/13/2015
Publication #:
Pub Dt:
05/19/2016
Title:
METHOD AND SYSTEM FOR COMPRESSING DATA FOR A TRANSLATION LOOK ASIDE BUFFER (TLB)
25
Patent #:
Issue Dt:
09/18/2018
Application #:
14940982
Filing Dt:
11/13/2015
Publication #:
Pub Dt:
05/19/2016
Title:
APPROACH FOR INTERFACING A PIPELINE WITH TWO OR MORE INTERFACES IN A PROCESSOR
26
Patent #:
Issue Dt:
06/13/2017
Application #:
14941082
Filing Dt:
11/13/2015
Publication #:
Pub Dt:
05/19/2016
Title:
DISTRIBUTING RESOURCE REQUESTS IN A COMPUTING SYSTEM
27
Patent #:
Issue Dt:
05/28/2019
Application #:
14941182
Filing Dt:
11/13/2015
Publication #:
Pub Dt:
05/19/2016
Title:
SHARING RESOURCES IN A MULTI-CONTEXT COMPUTING SYSTEM
28
Patent #:
Issue Dt:
09/26/2017
Application #:
15598719
Filing Dt:
05/18/2017
Publication #:
Pub Dt:
09/07/2017
Title:
METHOD AND SYSTEM FOR COMPRESSING DATA FOR A TRANSLATION LOOK ASIDE BUFFER (TLB)
29
Patent #:
Issue Dt:
12/08/2020
Application #:
15608852
Filing Dt:
05/30/2017
Publication #:
Pub Dt:
12/06/2018
Title:
FLOWLET SCHEDULER FOR MULTICORE NETWORK PROCESSORS
30
Patent #:
Issue Dt:
04/26/2022
Application #:
15875611
Filing Dt:
01/19/2018
Publication #:
Pub Dt:
07/25/2019
Title:
ISSUING INSTRUCTIONS BASED ON RESOURCE CONFLICT CONSTRAINTS IN MICROPORCESSOR
31
Patent #:
Issue Dt:
12/01/2020
Application #:
15894732
Filing Dt:
02/12/2018
Publication #:
Pub Dt:
12/13/2018
Title:
TIMESTAMP-BASED PACKET SWITCHING USING A TRIE DATA STRUCTURE
32
Patent #:
Issue Dt:
05/12/2020
Application #:
15934804
Filing Dt:
03/23/2018
Publication #:
Pub Dt:
09/26/2019
Title:
EXTERNAL DQS BI-DIRECTIONAL LOOPBACK WITH USE OF FEED FORWARD EQUALIZATION PATH
33
Patent #:
Issue Dt:
09/17/2019
Application #:
16039922
Filing Dt:
07/19/2018
Title:
WRITE AND READ COMMON LEVELING FOR 4-BIT WIDE DRAMS
34
Patent #:
Issue Dt:
12/03/2019
Application #:
16040249
Filing Dt:
07/19/2018
Title:
WRITE AND READ COMMON LEVELING FOR 4-BIT WIDE DRAMS
35
Patent #:
Issue Dt:
06/30/2020
Application #:
16054627
Filing Dt:
08/03/2018
Publication #:
Pub Dt:
02/06/2020
Title:
VOQ-BASED NETWORK SWITCH ARCHITECTURE USING MULTI-STAGE ARBITRATION FABRIC SCHEDULER
36
Patent #:
Issue Dt:
06/16/2020
Application #:
16115117
Filing Dt:
08/28/2018
Publication #:
Pub Dt:
03/05/2020
Title:
COMPRESSING LIKE MAGNITUDE PARTIAL PRODUCTS IN MULTIPLY ACCUMULATION
37
Patent #:
Issue Dt:
02/11/2020
Application #:
16128369
Filing Dt:
09/11/2018
Title:
METHODS AND SYSTEMS FOR DISTRIBUTING MEMORY REQUESTS
Assignor
1
Exec Dt:
09/21/2018
Assignee
1
2315 N. FIRST STREET
SAN JOSE, CALIFORNIA 95131
Correspondence name and address
MURABITO HAO & BARNES LLP
TWO NORTH MARKET STREET
THIRD FLOOR
SAN JOSE, CA 95113

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