Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Reel/Frame: | 020980/0693 | |
| Pages: | 2 |
| | Recorded: | 05/21/2008 | | |
Attorney Dkt #: | 190068/US |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
Total properties:
1
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
10933204
|
Filing Dt:
|
09/02/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
DELAY LOCK LOOP PHASE GLITCH ERROR FILTER
|
|
Assignee
|
|
|
8000 S FEDERAL WAY |
BOISE, IDAHO 83706 |
|
Correspondence name and address
|
|
DORSEY & WHITNEY LLP
|
|
US BANK CENTRE, 1420 5TH AVE. SUITE 3400
|
|
ATTN: EDWARD W. BULCHIS
|
|
SEATTLE, WA 98101-4010
|
Search Results as of:
05/30/2024 08:51 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|