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Reel/Frame:037558/0711   Pages: 101
Recorded: 01/19/2016
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 1256
Page 10 of 13
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13
1
Patent #:
Issue Dt:
04/19/2011
Application #:
11957506
Filing Dt:
12/17/2007
Publication #:
Pub Dt:
06/19/2008
Title:
VOLTAGE RANGE EXTENDER MECHANISM
2
Patent #:
Issue Dt:
04/21/2009
Application #:
11961134
Filing Dt:
12/20/2007
Title:
NON-VOLATILE MEMORY WITH SOURCE-SIDE COLUMN SELECT
3
Patent #:
Issue Dt:
03/15/2011
Application #:
11961176
Filing Dt:
12/20/2007
Publication #:
Pub Dt:
06/25/2009
Title:
BOOST CONVERTER WITH ADAPTIVE COIL PEAK CURRENT
4
Patent #:
Issue Dt:
04/13/2010
Application #:
11961203
Filing Dt:
12/20/2007
Title:
NON-VOLATILE MEMORY ARRAY HAVING DRAIN-SIDE SEGMENTATION FOR AN FPGA DEVICE
5
Patent #:
Issue Dt:
03/10/2009
Application #:
11962615
Filing Dt:
12/21/2007
Publication #:
Pub Dt:
04/24/2008
Title:
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
6
Patent #:
Issue Dt:
02/16/2010
Application #:
11962922
Filing Dt:
12/21/2007
Title:
FLEXIBLE CARRY SCHEME FOR FIELD PROGRAMMABLE GATE ARRAYS
7
Patent #:
Issue Dt:
10/14/2008
Application #:
11973573
Filing Dt:
10/09/2007
Publication #:
Pub Dt:
05/08/2008
Title:
HIGH TEMPERATURE, HIGH VOLTAGE SIC VOID-LESS ELECTRONIC PACKAGE
8
Patent #:
Issue Dt:
07/20/2010
Application #:
12018863
Filing Dt:
01/24/2008
Publication #:
Pub Dt:
07/31/2008
Title:
ADDRESSABLE SERIAL PERIPHERAL INTERFACE
9
Patent #:
Issue Dt:
11/10/2009
Application #:
12022064
Filing Dt:
01/29/2008
Title:
RECONFIGURABLE DELTA SIGMA ANALOG-TO-DIGITAL CONVERTER AND CUSTOMIZED DIGITAL FILTERS WITH EMBEDDED FLASH FPGA AND FLASH MEMORY
10
Patent #:
Issue Dt:
08/14/2012
Application #:
12022721
Filing Dt:
01/30/2008
Title:
FAST CARRY LOOKAHEAD CIRCUITS
11
Patent #:
Issue Dt:
06/16/2009
Application #:
12022921
Filing Dt:
01/30/2008
Title:
ISOLATION SCHEME FOR STATIC AND DYNAMIC FPGA PARTIAL PROGRAMMING
12
Patent #:
Issue Dt:
03/23/2010
Application #:
12023299
Filing Dt:
01/31/2008
Title:
PROGRAMMABLE LOGIC DEVICE WITH A MICROCONTROLLER-BASED CONTROL SYSTEM
13
Patent #:
Issue Dt:
11/24/2009
Application #:
12024867
Filing Dt:
02/01/2008
Publication #:
Pub Dt:
06/12/2008
Title:
PROGRAMMING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY-BASED PROGRAMMABLE LOGIC DEVICE
14
Patent #:
Issue Dt:
07/14/2009
Application #:
12028615
Filing Dt:
02/08/2008
Publication #:
Pub Dt:
05/29/2008
Title:
INTEGRATED CIRCUIT DEVICE HAVING STATE-SAVING AND INITIALIZATION FEATURE
15
Patent #:
Issue Dt:
12/15/2009
Application #:
12028692
Filing Dt:
02/08/2008
Title:
HIGH-VOLTAGE DUAL-POLARITY I/O P-WELL PUMP ESD PROTECTION CIRCUIT
16
Patent #:
NONE
Issue Dt:
Application #:
12029195
Filing Dt:
02/11/2008
Publication #:
Pub Dt:
08/13/2009
Title:
SYSTEM AND METHOD FOR DETECTING EARLY LINK FAILURE IN AN ETHERNET NETWORK
17
Patent #:
Issue Dt:
05/15/2012
Application #:
12029230
Filing Dt:
02/11/2008
Publication #:
Pub Dt:
08/13/2009
Title:
SYSTEM AND METHOD FOR SQUELCHING A RECOVERED CLOCK IN AN ETHERNET NETWORK
18
Patent #:
NONE
Issue Dt:
Application #:
12030907
Filing Dt:
02/14/2008
Publication #:
Pub Dt:
11/27/2008
Title:
FIXING APPARATUS AND AN IMAGE FORMATION APPARATUS
19
Patent #:
Issue Dt:
07/07/2009
Application #:
12034555
Filing Dt:
02/20/2008
Publication #:
Pub Dt:
06/12/2008
Title:
BLOCK LEVEL ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY
20
Patent #:
Issue Dt:
07/06/2010
Application #:
12038546
Filing Dt:
02/27/2008
Publication #:
Pub Dt:
08/27/2009
Title:
COAXIAL-TO-MICROSTRIP TRANSITIONS AND MANUFACTURING METHODS
21
Patent #:
Issue Dt:
12/20/2011
Application #:
12043246
Filing Dt:
03/06/2008
Publication #:
Pub Dt:
09/10/2009
Title:
MIRROR SCANNING SYSTEM
22
Patent #:
Issue Dt:
02/03/2009
Application #:
12045424
Filing Dt:
03/10/2008
Publication #:
Pub Dt:
06/26/2008
Title:
RADIATION TOLERANT SRAM BIT
23
Patent #:
Issue Dt:
01/13/2009
Application #:
12046160
Filing Dt:
03/11/2008
Publication #:
Pub Dt:
06/26/2008
Title:
THREE INPUT FIELD PROGRAMMABLE GATE ARRAY LOGIC CIRCUIT CONFIGURABLE AS A THREE INPUT LOOK UP TABLE, A D-LATCH OR A D FLIP- FLOP
24
Patent #:
Issue Dt:
03/15/2011
Application #:
12046642
Filing Dt:
03/12/2008
Publication #:
Pub Dt:
09/17/2009
Title:
PROTECTION CIRCUIT FOR A SUBSCRIBER LINE INTERFACE CIRCUIT
25
Patent #:
Issue Dt:
05/11/2010
Application #:
12046683
Filing Dt:
03/12/2008
Publication #:
Pub Dt:
09/17/2009
Title:
OPTICALLY TRIGGERED ELECTRO-STATIC DISCHARGE PROTECTION CIRCUIT
26
Patent #:
Issue Dt:
06/16/2009
Application #:
12049410
Filing Dt:
03/17/2008
Publication #:
Pub Dt:
10/02/2008
Title:
COLOR CONTROL FOR DYNAMIC SCANNING BACKLIGHT
27
Patent #:
Issue Dt:
11/23/2010
Application #:
12054633
Filing Dt:
03/25/2008
Publication #:
Pub Dt:
07/17/2008
Title:
NON-VOLATILE PROGRAMMABLE MEMORY CELL AND ARRAY FOR PROGRAMMABLE LOGIC ARRAY
28
Patent #:
Issue Dt:
10/26/2010
Application #:
12061085
Filing Dt:
04/02/2008
Publication #:
Pub Dt:
10/08/2009
Title:
LIGHT ACTIVATED SILICON CONTROLLED SWITCH
29
Patent #:
Issue Dt:
10/26/2010
Application #:
12061085
Filing Dt:
04/02/2008
Publication #:
Pub Dt:
10/08/2009
Title:
LIGHT ACTIVATED SILICON CONTROLLED SWITCH
30
Patent #:
Issue Dt:
10/11/2011
Application #:
12061264
Filing Dt:
04/02/2008
Publication #:
Pub Dt:
10/08/2009
Title:
METHODS OF COUNTER-DOPING COLLECTOR REGIONS IN BIPOLAR TRANSISTORS
31
Patent #:
Issue Dt:
10/11/2011
Application #:
12061264
Filing Dt:
04/02/2008
Publication #:
Pub Dt:
10/08/2009
Title:
METHODS OF COUNTER-DOPING COLLECTOR REGIONS IN BIPOLAR TRANSISTORS
32
Patent #:
Issue Dt:
08/10/2010
Application #:
12101589
Filing Dt:
04/11/2008
Title:
LOGIC MODULE INCLUDING VERSATILE ADDER FOR FPGA
33
Patent #:
Issue Dt:
06/09/2009
Application #:
12105524
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
08/14/2008
Title:
CLOCK TREE NETWORK IN A FIELD PROGRAMMABLE GATE ARRAY
34
Patent #:
Issue Dt:
06/09/2009
Application #:
12109487
Filing Dt:
04/25/2008
Publication #:
Pub Dt:
08/21/2008
Title:
FIELD-PROGRAMMABLE GATE ARRAY LOW VOLTAGE DIFFERENTIAL SIGNALING DRIVER UTILIZING TWO COMPLIMENTARY OUTPUT BUFFERS
35
Patent #:
Issue Dt:
08/24/2010
Application #:
12110508
Filing Dt:
04/28/2008
Publication #:
Pub Dt:
10/30/2008
Title:
SYSTEM AND METHOD FOR MANIPULATING REAL-TIME VIDEO PLAYBACK TIME-SYNCHRONIZED WITH MILLIMETER WAVE IMAGERY
36
Patent #:
NONE
Issue Dt:
Application #:
12110520
Filing Dt:
04/28/2008
Publication #:
Pub Dt:
10/30/2008
Title:
SYSTEM FOR DEPLOYMENT OF A MILLIMETER WAVE CONCEALED OBJECT DETECTION SYSTEM
37
Patent #:
Issue Dt:
07/13/2010
Application #:
12111660
Filing Dt:
04/29/2008
Publication #:
Pub Dt:
08/21/2008
Title:
ENHANCED FIELD PROGRAMMABLE GATE ARRAY
38
Patent #:
Issue Dt:
03/24/2015
Application #:
12114143
Filing Dt:
05/02/2008
Publication #:
Pub Dt:
08/28/2008
Title:
DEDICATED INTERFACE ARCHITECTURE FOR A HYBRID INTEGRATED CIRCUIT
39
Patent #:
Issue Dt:
03/24/2015
Application #:
12114143
Filing Dt:
05/02/2008
Publication #:
Pub Dt:
08/28/2008
Title:
DEDICATED INTERFACE ARCHITECTURE FOR A HYBRID INTEGRATED CIRCUIT
40
Patent #:
Issue Dt:
12/18/2012
Application #:
12117779
Filing Dt:
05/09/2008
Publication #:
Pub Dt:
12/04/2008
Title:
DOUBLE TALK DETECTION METHOD BASED ON SPECTRAL ACOUSTIC PROPERTIES
41
Patent #:
Issue Dt:
10/11/2011
Application #:
12118960
Filing Dt:
05/12/2008
Publication #:
Pub Dt:
01/15/2009
Title:
PASSIVE OUTDOOR MILLIMETER WAVE ILLUMINATOR
42
Patent #:
Issue Dt:
10/20/2009
Application #:
12122771
Filing Dt:
05/19/2008
Title:
INTEGRATED SILICON OPTICAL ISOLATOR
43
Patent #:
Issue Dt:
08/03/2010
Application #:
12124661
Filing Dt:
05/21/2008
Title:
RADIATION-TOLERANT FLASH-BASED FPGA MEMORY CELLS
44
Patent #:
Issue Dt:
04/17/2012
Application #:
12127818
Filing Dt:
05/28/2008
Publication #:
Pub Dt:
12/03/2009
Title:
ECHO CANCELLATION BALANCE USING NOISE GENERATOR AND AVERAGE POWER DETECTION
45
Patent #:
Issue Dt:
07/07/2009
Application #:
12130876
Filing Dt:
05/30/2008
Publication #:
Pub Dt:
10/23/2008
Title:
BLOCK SYMMETRIZATION IN A FIELD PROGRAMMABLE GATE ARRAY
46
Patent #:
Issue Dt:
08/25/2009
Application #:
12131258
Filing Dt:
06/02/2008
Publication #:
Pub Dt:
10/09/2008
Title:
REPEATABLE BLOCK PRODUCING A NON-UNIFORM ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY HAVING SEGMENTED TRACKS
47
Patent #:
Issue Dt:
03/09/2010
Application #:
12131377
Filing Dt:
06/02/2008
Publication #:
Pub Dt:
09/18/2008
Title:
NON-VOLATILE MEMORY ARCHITECTURE FOR PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
48
Patent #:
Issue Dt:
11/06/2012
Application #:
12131539
Filing Dt:
06/02/2008
Publication #:
Pub Dt:
12/04/2008
Title:
METHOD AND SYSTEM FOR DYNAMICALLY ALTERING THE ANALYSIS METHODOLOGY OF MILLIMETER WAVE IMAGERY IN RESPONSE TO THE RANGE AND DIRECTION OF MOTION OF A SUBJECT
49
Patent #:
Issue Dt:
12/28/2010
Application #:
12135698
Filing Dt:
06/09/2008
Publication #:
Pub Dt:
06/04/2009
Title:
SYSTEM FOR DEPLOYMENT OF A MILLIMETER WAVE CONCEALED OBJECT DETECTION SYSTEM USING AN OUTDOOR PASSIVELY ILLUMINATED STRUCTURE
50
Patent #:
Issue Dt:
11/22/2011
Application #:
12136000
Filing Dt:
06/09/2008
Publication #:
Pub Dt:
12/11/2008
Title:
STRUCTURAL SYSTEM FOR OPTIMIZING PERFORMANCE OF A MILLIMETER WAVE CONCEALED OBJECT DETECTION SYSTEM
51
Patent #:
Issue Dt:
11/24/2009
Application #:
12136092
Filing Dt:
06/10/2008
Publication #:
Pub Dt:
01/01/2009
Title:
BRIGHTNESS CONTROL FOR DYNAMIC SCANNING BACKLIGHT
52
Patent #:
Issue Dt:
10/12/2010
Application #:
12136095
Filing Dt:
06/10/2008
Publication #:
Pub Dt:
01/01/2009
Title:
INTEGRATED SYNCHRONIZED OPTICAL SAMPLING AND CONTROL ELEMENT
53
Patent #:
Issue Dt:
02/23/2010
Application #:
12139354
Filing Dt:
06/13/2008
Title:
MIXED SIGNAL SYSTEM-ON-A-CHIP INTEGRATED SIMULTANEOUS MULTIPLE SAMPLE/HOLD CIRCUITS AND EMBEDDED ANALOG COMPARATORS
54
Patent #:
Issue Dt:
04/26/2011
Application #:
12142118
Filing Dt:
06/19/2008
Title:
STAGGERED I/O GROUPS FOR INTEGRATED CIRCUITS
55
Patent #:
Issue Dt:
02/14/2012
Application #:
12142982
Filing Dt:
06/20/2008
Publication #:
Pub Dt:
03/05/2009
Title:
SYSTEM AND METHOD FOR OVERLAYING COMPUTER GENERATED HIGHLIGHTS IN A DISPLAY OF MILLIMETER WAVE IMAGERY
56
Patent #:
Issue Dt:
04/19/2011
Application #:
12170448
Filing Dt:
07/10/2008
Publication #:
Pub Dt:
01/22/2009
Title:
METHOD OF SAMPLING A MODULATED SIGNAL DRIVEN CHANNEL
57
Patent #:
Issue Dt:
09/18/2012
Application #:
12172532
Filing Dt:
07/14/2008
Publication #:
Pub Dt:
01/14/2010
Title:
A TRENCH CAPACITOR FOR HIGH VOLTAGE PROCESSES AND METHOD OF MANUFACTURING THE SAME
58
Patent #:
Issue Dt:
05/26/2009
Application #:
12172675
Filing Dt:
07/14/2008
Title:
CIRCUIT AND METHOD FOR SUPPLYING PROGRAMMING POTENTIAL AT VOLTAGES LARGER THAN BVDSS OF PROGRAMMING TRANSISTORS
59
Patent #:
Issue Dt:
03/02/2010
Application #:
12172860
Filing Dt:
07/14/2008
Publication #:
Pub Dt:
12/04/2008
Title:
DEGLITCHING CIRCUITS FOR A RADIATION-HARDENED STATIC RANDOM ACCESS MEMORY BASED PROGRAMMABLE ARCHITECTURE
60
Patent #:
Issue Dt:
07/07/2009
Application #:
12173117
Filing Dt:
07/15/2008
Publication #:
Pub Dt:
10/30/2008
Title:
SRAM CELL CONTROLLED BY FLASH MEMORY CELL
61
Patent #:
Issue Dt:
06/09/2009
Application #:
12173225
Filing Dt:
07/15/2008
Title:
FPGA ARCHITECTURE HAVING TWO-LEVEL CLUSTER INPUT INTERCONNECT SCHEME WITHOUT BANDWIDTH LIMITATION
62
Patent #:
Issue Dt:
04/20/2010
Application #:
12175399
Filing Dt:
07/17/2008
Title:
PROGRAMMABLE DELAY LINE COMPENSATED FOR PROCESS, VOLTAGE, AND TEMPERATURE
63
Patent #:
Issue Dt:
11/10/2009
Application #:
12176560
Filing Dt:
07/21/2008
Publication #:
Pub Dt:
11/06/2008
Title:
SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT INCLUDING DUAL-FUNCTION ANALOG AND DIGITAL INPUTS
64
Patent #:
Issue Dt:
04/06/2010
Application #:
12177680
Filing Dt:
07/22/2008
Title:
SPLIT GATE MEMORY CELL FOR PROGRAMMABLE CIRCUIT DEVICE
65
Patent #:
Issue Dt:
07/14/2009
Application #:
12178874
Filing Dt:
07/24/2008
Publication #:
Pub Dt:
12/11/2008
Title:
PROGRAMMABLE SYSTEM ON A CHIP FOR TEMPERATURE MONITORING AND CONTROL
66
Patent #:
Issue Dt:
02/09/2010
Application #:
12179243
Filing Dt:
07/24/2008
Publication #:
Pub Dt:
12/04/2008
Title:
ESD PROTECTION STRUCTURE FOR I/O PAD SUBJECT TO BOTH POSITIVE AND NEGATIVE VOLTAGES
67
Patent #:
NONE
Issue Dt:
Application #:
12181533
Filing Dt:
07/29/2008
Publication #:
Pub Dt:
02/04/2010
Title:
Method and Apparatus for Secure Data Storage System
68
Patent #:
Issue Dt:
02/09/2010
Application #:
12187541
Filing Dt:
08/07/2008
Title:
QUADRATIC AND CUBIC COMPENSATION OF SIGMA-DELTA D/A AND A/D CONVERTERS
69
Patent #:
Issue Dt:
08/23/2011
Application #:
12190907
Filing Dt:
08/13/2008
Publication #:
Pub Dt:
02/18/2010
Title:
BOOTSTRAP SUPPLY FOR SWITCHED MODE POWER CONVERTER
70
Patent #:
Issue Dt:
03/15/2011
Application #:
12196978
Filing Dt:
08/22/2008
Publication #:
Pub Dt:
02/25/2010
Title:
REDUCED-EDGE RADIATION-TOLERANT NON-VOLATILE TRANSISTOR MEMORY CELLS
71
Patent #:
Issue Dt:
08/10/2010
Application #:
12198249
Filing Dt:
08/26/2008
Publication #:
Pub Dt:
02/19/2009
Title:
APPARATUS FOR TESTING A PHRASE-LOCKED LOOP IN A BOUNDARY SCAN ENABLED DEVICE
72
Patent #:
Issue Dt:
09/28/2010
Application #:
12205656
Filing Dt:
09/05/2008
Publication #:
Pub Dt:
03/11/2010
Title:
CIRCUITS AND METHODS FOR TESTING FPGA ROUTING SWITCHES
73
Patent #:
Issue Dt:
02/07/2012
Application #:
12206954
Filing Dt:
09/09/2008
Publication #:
Pub Dt:
03/19/2009
Title:
EDGE TERMINATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICE
74
Patent #:
Issue Dt:
11/23/2010
Application #:
12207321
Filing Dt:
09/09/2008
Publication #:
Pub Dt:
03/11/2010
Title:
FUSES FOR MEMORY REPAIR
75
Patent #:
Issue Dt:
01/03/2012
Application #:
12207686
Filing Dt:
09/10/2008
Publication #:
Pub Dt:
03/26/2009
Title:
DIGITAL FM RADIO TRANSMITTER
76
Patent #:
Issue Dt:
01/12/2010
Application #:
12215118
Filing Dt:
06/24/2008
Publication #:
Pub Dt:
10/30/2008
Title:
ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS
77
Patent #:
Issue Dt:
10/26/2010
Application #:
12239418
Filing Dt:
09/26/2008
Publication #:
Pub Dt:
04/01/2010
Title:
DIFFERENTIAL VOLTAGE MODE DRIVER AND DIGITAL IMPEDANCE CALIBERATION OF SAME
78
Patent #:
Issue Dt:
09/04/2012
Application #:
12263628
Filing Dt:
11/03/2008
Publication #:
Pub Dt:
05/06/2010
Title:
METHOD AND APPARATUS FOR METALLIC LINE TESTING OF A SUBSCRIBER LINE
79
Patent #:
Issue Dt:
05/18/2010
Application #:
12269798
Filing Dt:
11/12/2008
Publication #:
Pub Dt:
05/13/2010
Title:
METHOD AND APPARATUS FOR STACKED DIE PACKAGE WITH INSULATED WIRE BONDS
80
Patent #:
Issue Dt:
09/25/2012
Application #:
12270774
Filing Dt:
11/13/2008
Publication #:
Pub Dt:
05/13/2010
Title:
CONTINUOUSLY INTERLEAVED ERROR CORRECTION
81
Patent #:
Issue Dt:
09/13/2011
Application #:
12315741
Filing Dt:
12/05/2008
Publication #:
Pub Dt:
05/28/2009
Title:
INTEGRATED CIRCUIT WITH FLEXIBLE PLANAR LEADS
82
Patent #:
Issue Dt:
11/23/2010
Application #:
12334059
Filing Dt:
12/12/2008
Publication #:
Pub Dt:
06/17/2010
Title:
PUSH-PULL FPGA CELL
83
Patent #:
Issue Dt:
07/17/2012
Application #:
12336990
Filing Dt:
12/17/2008
Publication #:
Pub Dt:
04/09/2009
Title:
METHOD AND APPARATUS TO CONTROL DISPLAY BRIGHTNESS WITH AMBIENT LIGHT CORRECTION
84
Patent #:
Issue Dt:
05/10/2011
Application #:
12337201
Filing Dt:
12/17/2008
Publication #:
Pub Dt:
04/09/2009
Title:
DELAY LOCKED LOOP FOR AN FPGA ARCHITECTURE
85
Patent #:
Issue Dt:
10/01/2013
Application #:
12338780
Filing Dt:
12/18/2008
Publication #:
Pub Dt:
07/23/2009
Title:
INCLUSION OF ASSESSMENT DATA IN MILLIMETER WAVE CONCEALED OBJECT DETECTION SYSTEMS
86
Patent #:
Issue Dt:
05/07/2013
Application #:
12338807
Filing Dt:
12/18/2008
Publication #:
Pub Dt:
12/03/2009
Title:
SOFTWARE METHODOLOGY FOR AUTONOMOUS CONCEALED OBJECT DETECTION AND THREAT ASSESSMENT
87
Patent #:
Issue Dt:
02/08/2011
Application #:
12340358
Filing Dt:
12/19/2008
Publication #:
Pub Dt:
06/24/2010
Title:
PLD PROVIDING SOFT WAKEUP LOGIC
88
Patent #:
Issue Dt:
10/18/2011
Application #:
12340440
Filing Dt:
12/19/2008
Publication #:
Pub Dt:
06/24/2010
Title:
PROGRAMMABLE LOGIC DEVICE WITH PROGRAMMABLE WAKEUP PINS
89
Patent #:
Issue Dt:
03/15/2011
Application #:
12340717
Filing Dt:
12/21/2008
Publication #:
Pub Dt:
07/16/2009
Title:
FINE TUNED MULTIPLE OUTPUT CONVERTER
90
Patent #:
Issue Dt:
04/19/2011
Application #:
12343308
Filing Dt:
12/23/2008
Publication #:
Pub Dt:
06/24/2010
Title:
PUSH-PULL MEMORY CELL CONFIGURED FOR SIMULTANEOUS PROGRAMMING OF N-CHANNEL AND P-CHANNEL NON-VOLATILE TRANSISTORS
91
Patent #:
Issue Dt:
08/03/2010
Application #:
12345388
Filing Dt:
12/29/2008
Publication #:
Pub Dt:
06/04/2009
Title:
RADIATION TOLERANT SRAM BIT
92
Patent #:
Issue Dt:
02/08/2011
Application #:
12345409
Filing Dt:
12/29/2008
Publication #:
Pub Dt:
04/23/2009
Title:
FIELD PROGRAMMABLE GATE ARRAY AND MICROCONTROLLER SYSTEM-ON-A-CHIP
93
Patent #:
NONE
Issue Dt:
Application #:
12348002
Filing Dt:
01/01/2009
Publication #:
Pub Dt:
07/23/2009
Title:
Low Voltage Drop Unidirectional Electronic Valve
94
Patent #:
Issue Dt:
10/13/2009
Application #:
12350419
Filing Dt:
01/08/2009
Publication #:
Pub Dt:
05/21/2009
Title:
PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL
95
Patent #:
Issue Dt:
08/10/2010
Application #:
12352512
Filing Dt:
01/12/2009
Publication #:
Pub Dt:
07/30/2009
Title:
SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS
96
Patent #:
Issue Dt:
03/01/2011
Application #:
12359481
Filing Dt:
01/26/2009
Publication #:
Pub Dt:
06/25/2009
Title:
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
97
Patent #:
Issue Dt:
10/19/2010
Application #:
12360948
Filing Dt:
01/28/2009
Title:
INVERTING FLIP-FLOP FOR USE IN FIELD PROGRAMMABLE GATE ARRAYS
98
Patent #:
Issue Dt:
04/20/2010
Application #:
12360971
Filing Dt:
01/28/2009
Title:
(N+1) INPUT FLIP-FLOP PACKING WITH LOGIC IN FPGA ARCHITECTURES
99
Patent #:
Issue Dt:
04/12/2011
Application #:
12361835
Filing Dt:
01/29/2009
Title:
FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE HAVING CLOS NETWORK-BASED INPUT INTERCONNECT
100
Patent #:
Issue Dt:
05/29/2012
Application #:
12361955
Filing Dt:
01/29/2009
Publication #:
Pub Dt:
08/13/2009
Title:
SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS
Assignor
1
Exec Dt:
01/15/2016
Assignees
1
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
2
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
3
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
4
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
5
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
6
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
7
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
Correspondence name and address
ELAINE CARRERA, LEGAL ASSISTANT
80 PINE STREET
C/O CAHILL GORDON & REINDEL LLP
NEW YORK, NY 10005

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