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Reel/Frame:037558/0711   Pages: 101
Recorded: 01/19/2016
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 1256
Page 13 of 13
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13
1
Patent #:
Issue Dt:
06/16/2015
Application #:
13894638
Filing Dt:
05/15/2013
Publication #:
Pub Dt:
11/21/2013
Title:
METHOD OF ADJUSTING A LOCAL CLOCK IN ASYNCHRONOUS PACKET NETWORKS
2
Patent #:
Issue Dt:
10/06/2015
Application #:
13895236
Filing Dt:
05/15/2013
Publication #:
Pub Dt:
11/21/2013
Title:
INTEGRATED START-UP BIAS BOOST FOR DYNAMIC ERROR VECTOR MAGNITUDE ENHANCEMENT
3
Patent #:
NONE
Issue Dt:
Application #:
13895554
Filing Dt:
05/16/2013
Publication #:
Pub Dt:
11/28/2013
Title:
TID HARDENED MOS TRANSISTORS AND FABRICATION PROCESS
4
Patent #:
Issue Dt:
08/25/2015
Application #:
13897192
Filing Dt:
05/17/2013
Publication #:
Pub Dt:
11/21/2013
Title:
INTEGRATED START-UP BIAS BOOST FOR DYNAMIC ERROR VECTOR MAGNITUDE ENHANCEMENT
5
Patent #:
Issue Dt:
10/03/2017
Application #:
13898827
Filing Dt:
05/21/2013
Publication #:
Pub Dt:
10/17/2013
Title:
FPGA RAM BLOCKS OPTIMIZED FOR USE AS REGISTER FILES
6
Patent #:
NONE
Issue Dt:
Application #:
13902382
Filing Dt:
05/24/2013
Publication #:
Pub Dt:
11/28/2013
Title:
MONOLITHICALLY INTEGRATED SIC MOSFET AND SCHOTTKY BARRIER DIODE
7
Patent #:
NONE
Issue Dt:
Application #:
13921058
Filing Dt:
06/18/2013
Publication #:
Pub Dt:
12/18/2014
Title:
POWER CONVERTER
8
Patent #:
Issue Dt:
04/07/2015
Application #:
13933332
Filing Dt:
07/02/2013
Publication #:
Pub Dt:
01/02/2014
Title:
ON-CHIP PROBE CIRCUIT FOR DETECTING FAULTS IN AN FPGA
9
Patent #:
Issue Dt:
08/11/2015
Application #:
13933353
Filing Dt:
07/02/2013
Publication #:
Pub Dt:
01/02/2014
Title:
ON-CHIP PROBE CIRCUIT FOR DETECTING FAULTS IN AN FPGA
10
Patent #:
Issue Dt:
12/15/2015
Application #:
13943305
Filing Dt:
07/16/2013
Publication #:
Pub Dt:
01/23/2014
Title:
APPARATUS AND METHOD FOR SENSING INCIDENT LIGHT HAVING DUAL PHOTODIODE TO ABSORB LIGHT IN RESPECTIVE DEPLETION REGIONS CONTROLLED BY DIFFERENT BIAS VOLTAGES (AS AMENDED)
11
Patent #:
NONE
Issue Dt:
Application #:
13964692
Filing Dt:
08/12/2013
Publication #:
Pub Dt:
02/13/2014
Title:
SECURE DIGEST FOR PLD CONFIGURATION DATA
12
Patent #:
Issue Dt:
10/13/2015
Application #:
14013339
Filing Dt:
08/29/2013
Publication #:
Pub Dt:
03/20/2014
Title:
AUTO-REFRESH METHOD FOR SONOS NON-VOLATILE MEMORY ARRAY
13
Patent #:
Issue Dt:
01/26/2016
Application #:
14040320
Filing Dt:
09/27/2013
Publication #:
Pub Dt:
04/03/2014
Title:
DELAY MEASUREMENT IN A POINT TO MULTIPOINT SYSTEM
14
Patent #:
Issue Dt:
03/03/2015
Application #:
14041626
Filing Dt:
09/30/2013
Publication #:
Pub Dt:
04/03/2014
Title:
HIGH ACCURACY 1588 TIMESTAMPING OVER HIGH SPEED MULTI LANE DISTRIBUTION PHYSICAL CODE SUBLAYERS
15
Patent #:
Issue Dt:
05/26/2015
Application #:
14079541
Filing Dt:
11/13/2013
Publication #:
Pub Dt:
03/06/2014
Title:
LOW LOSS SIC MOSFET
16
Patent #:
Issue Dt:
09/09/2014
Application #:
14084720
Filing Dt:
11/20/2013
Publication #:
Pub Dt:
03/13/2014
Title:
INTEGRATED CIRCUIT PACKAGE
17
Patent #:
Issue Dt:
09/15/2015
Application #:
14090401
Filing Dt:
11/26/2013
Publication #:
Pub Dt:
06/12/2014
Title:
INTEGRATED START-UP BIAS BOOST FOR DYNAMIC ERROR VECTOR MAGNITUDE ENHANCEMENT
18
Patent #:
NONE
Issue Dt:
Application #:
14094816
Filing Dt:
12/03/2013
Publication #:
Pub Dt:
06/12/2014
Title:
METHOD OF MAINTAINING AN OUTPUT VOLTAGE OF A POWER CONVERTER
19
Patent #:
Issue Dt:
08/11/2015
Application #:
14135437
Filing Dt:
12/19/2013
Publication #:
Pub Dt:
12/04/2014
Title:
PARALLEL CRC COMPUTATION WITH DATA ENABLES
20
Patent #:
Issue Dt:
03/24/2015
Application #:
14143025
Filing Dt:
12/30/2013
Publication #:
Pub Dt:
07/17/2014
Title:
ON-CHIP PORT CURRENT CONTROL ARRANGEMENT
21
Patent #:
Issue Dt:
08/26/2014
Application #:
14143031
Filing Dt:
12/30/2013
Publication #:
Pub Dt:
07/17/2014
Title:
WIDE RANGE INPUT CURRENT CIRCUITRY FOR AN ANALOG TO DIGITAL CONVERTER
22
Patent #:
Issue Dt:
02/16/2016
Application #:
14149370
Filing Dt:
01/07/2014
Publication #:
Pub Dt:
07/10/2014
Title:
UNIVERSAL ASYMMETRY COMPENSATION FOR PACKET TIMING PROTOCOLS
23
Patent #:
Issue Dt:
09/05/2017
Application #:
14155752
Filing Dt:
01/15/2014
Publication #:
Pub Dt:
05/22/2014
Title:
NON-VOLATILE PROGRAMMABLE MEMORY CELL AND ARRAY FOR PROGRAMMABLE LOGIC ARRAY
24
Patent #:
Issue Dt:
08/23/2016
Application #:
14160449
Filing Dt:
01/21/2014
Publication #:
Pub Dt:
05/15/2014
Title:
TIMING SYNCHRONIZATION FOR NETWORKS WITH RADIO LINKS
25
Patent #:
NONE
Issue Dt:
Application #:
14171698
Filing Dt:
02/03/2014
Publication #:
Pub Dt:
01/01/2015
Title:
PACKET-BASED TIMING MEASUREMENT
26
Patent #:
NONE
Issue Dt:
Application #:
14171809
Filing Dt:
02/04/2014
Publication #:
Pub Dt:
08/07/2014
Title:
MULTIPLEXED SIGMA DELTA MODULATOR
27
Patent #:
Issue Dt:
06/07/2016
Application #:
14171843
Filing Dt:
02/04/2014
Publication #:
Pub Dt:
08/07/2014
Title:
HYSTERETIC CURRENT MODE CONTROL CONVERTER WITH LOW, MEDIUM AND HIGH CURRENT THRESHOLDS
28
Patent #:
Issue Dt:
10/06/2015
Application #:
14188398
Filing Dt:
02/24/2014
Publication #:
Pub Dt:
08/28/2014
Title:
DISTRIBUTION OF LOCATION INFORMATION
29
Patent #:
Issue Dt:
03/15/2016
Application #:
14193772
Filing Dt:
02/28/2014
Publication #:
Pub Dt:
09/04/2014
Title:
NON-VOLATILE PUSH-PULL NON-VOLATILE MEMORY CELL HAVING REDUCED OPERATION DISTURB AND PROCESS FOR MANUFACTURING SAME
30
Patent #:
Issue Dt:
07/28/2015
Application #:
14196667
Filing Dt:
03/04/2014
Publication #:
Pub Dt:
10/02/2014
Title:
TID HARDENED AND SINGLE EVENT TRANSIENT SINGLE EVENT LATCHUP RESISTANT MOS TRANSISTORS AND FABRICATION PROCESS
31
Patent #:
Issue Dt:
04/26/2016
Application #:
14208513
Filing Dt:
03/13/2014
Publication #:
Pub Dt:
09/18/2014
Title:
Background Auto-refresh Apparatus and Method for Non-Volatile Memory Array
32
Patent #:
Issue Dt:
07/04/2017
Application #:
14210913
Filing Dt:
03/14/2014
Publication #:
Pub Dt:
09/18/2014
Title:
DISTRIBUTED TWO-STEP CLOCK
33
Patent #:
Issue Dt:
12/06/2016
Application #:
14212508
Filing Dt:
03/14/2014
Publication #:
Pub Dt:
09/18/2014
Title:
System on a Chip FPGA Spatial Debugging Using Single Snapshot
34
Patent #:
Issue Dt:
01/22/2019
Application #:
14250059
Filing Dt:
04/10/2014
Publication #:
Pub Dt:
12/11/2014
Title:
CHIP-SCALE ATOMIC GYROSCOPE
35
Patent #:
Issue Dt:
10/06/2015
Application #:
14258775
Filing Dt:
04/22/2014
Publication #:
Pub Dt:
10/30/2014
Title:
VOIDLESSLY ENCAPSULATED SEMICONDUCTOR DIE PACKAGE
36
Patent #:
Issue Dt:
02/17/2015
Application #:
14263170
Filing Dt:
04/28/2014
Publication #:
Pub Dt:
10/30/2014
Title:
PHASE LOCKED LOOP WITH PRECISE PHASE AND FREQUENCY SLOPE LIMITER
37
Patent #:
Issue Dt:
12/09/2014
Application #:
14263286
Filing Dt:
04/28/2014
Publication #:
Pub Dt:
10/30/2014
Title:
PHASE LOCKED LOOP WITH SIMULTANEOUS LOCKING TO LOW AND HIGH FREQUENCY CLOCKS
38
Patent #:
Issue Dt:
03/17/2015
Application #:
14274417
Filing Dt:
05/09/2014
Publication #:
Pub Dt:
09/04/2014
Title:
Back to Back Resistive Random Access Memory Cells
39
Patent #:
Issue Dt:
01/27/2015
Application #:
14311638
Filing Dt:
06/23/2014
Publication #:
Pub Dt:
01/01/2015
Title:
DIGITAL PHASE LOCKED LOOP WITH REDUCED CONVERGENCE TIME
40
Patent #:
Issue Dt:
04/24/2018
Application #:
14322953
Filing Dt:
07/03/2014
Publication #:
Pub Dt:
01/08/2015
Title:
METHOD FOR SECURELY BOOTING TARGET PROCESSOR IN TARGET SYSTEM USING A SECURE ROOT OF TRUST TO VERIFY A RETURNED MESSAGE AUTHENTICATION CODE RECREATED BY THE TARGET PROCESSOR
41
Patent #:
Issue Dt:
09/29/2015
Application #:
14327842
Filing Dt:
07/10/2014
Publication #:
Pub Dt:
01/15/2015
Title:
METHOD FOR EFFICIENT FPGA PACKING
42
Patent #:
Issue Dt:
03/28/2017
Application #:
14337256
Filing Dt:
07/22/2014
Publication #:
Pub Dt:
01/29/2015
Title:
INTEGRATED LIMITER AND ACTIVE FILTER
43
Patent #:
NONE
Issue Dt:
Application #:
14337865
Filing Dt:
07/22/2014
Publication #:
Pub Dt:
11/20/2014
Title:
PSEUDO SELF ALIGNED RADHARD MOSFET AND PROCESS OF MANUFACTURE
44
Patent #:
Issue Dt:
06/11/2019
Application #:
14454134
Filing Dt:
08/07/2014
Publication #:
Pub Dt:
02/12/2015
Title:
VOLTAGE REGULATOR WITH SWITCHING AND LOW DROPOUT MODES
45
Patent #:
Issue Dt:
03/14/2017
Application #:
14482527
Filing Dt:
09/10/2014
Publication #:
Pub Dt:
03/12/2015
Title:
RADIO WAKE-UP SYSTEM WITH MULTI-MODE OPERATION
46
Patent #:
Issue Dt:
08/02/2016
Application #:
14482595
Filing Dt:
09/10/2014
Publication #:
Pub Dt:
03/12/2015
Title:
MULTI-CHANNEL LOW POWER WAKE-UP SYSTEM
47
Patent #:
NONE
Issue Dt:
Application #:
14494438
Filing Dt:
09/23/2014
Publication #:
Pub Dt:
01/08/2015
Title:
PACKET PROTOCOL PROCESSING WITH PRECISION TIMING PROTOCOL SUPPORT
48
Patent #:
Issue Dt:
08/30/2016
Application #:
14502877
Filing Dt:
09/30/2014
Publication #:
Pub Dt:
04/02/2015
Title:
PTP TRANSPARENT CLOCK SYSTEM UPGRADE SOLUTION
49
Patent #:
Issue Dt:
01/02/2018
Application #:
14503082
Filing Dt:
09/30/2014
Publication #:
Pub Dt:
01/15/2015
Title:
NETWORK DISTRIBUTED PACKET-BASED SYNCHRONIZATION
50
Patent #:
Issue Dt:
09/08/2015
Application #:
14526148
Filing Dt:
10/28/2014
Publication #:
Pub Dt:
02/12/2015
Title:
CONTINUOUSLY INTERLEAVED ERROR CORRECTION
51
Patent #:
Issue Dt:
06/17/2008
Application #:
29283233
Filing Dt:
08/08/2007
Title:
SECURITY SYSTEM HOUSING
52
Patent #:
Issue Dt:
03/15/2011
Application #:
29306747
Filing Dt:
04/15/2008
Title:
SECURITY SYSTEM HOUSING
53
Patent #:
Issue Dt:
06/22/2010
Application #:
29306748
Filing Dt:
04/15/2008
Title:
PEDESTAL MOUNT FOR SECURITY CAMERA
54
Patent #:
Issue Dt:
03/26/2013
Application #:
29379049
Filing Dt:
11/30/2010
Title:
MOBILE SECURITY SYSTEM HOUSING
55
Patent #:
Issue Dt:
07/17/2012
Application #:
29385707
Filing Dt:
02/18/2011
Title:
HAND HELD SCANNER
56
Patent #:
Issue Dt:
06/19/2012
Application #:
29385710
Filing Dt:
02/18/2011
Title:
SECURITY SYSTEM PORTAL
Assignor
1
Exec Dt:
01/15/2016
Assignees
1
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
2
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
3
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
4
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
5
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
6
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
7
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
Correspondence name and address
ELAINE CARRERA, LEGAL ASSISTANT
80 PINE STREET
C/O CAHILL GORDON & REINDEL LLP
NEW YORK, NY 10005

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