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Reel/Frame:037558/0711   Pages: 101
Recorded: 01/19/2016
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 1256
Page 8 of 13
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13
1
Patent #:
Issue Dt:
11/28/2006
Application #:
10970244
Filing Dt:
10/20/2004
Publication #:
Pub Dt:
05/05/2005
Title:
SYSTEMS AND METHODS FOR A TRANSFORMER CONFIGURATION FOR DRIVING MULTIPLE GAS DISCHARGE TUBES IN PARALLEL
2
Patent #:
Issue Dt:
10/09/2007
Application #:
10970248
Filing Dt:
10/20/2004
Publication #:
Pub Dt:
05/05/2005
Title:
SYSTEMS AND METHODS FOR FAULT PROTECTION IN A BALANCING TRANSFORMER
3
Patent #:
Issue Dt:
03/24/2009
Application #:
10997057
Filing Dt:
11/24/2004
Publication #:
Pub Dt:
11/24/2005
Title:
METHOD OF FABRICATING SELF-ALIGNED SILICON CARBIDE SEMICONDUCTOR DEVICES
4
Patent #:
Issue Dt:
07/24/2007
Application #:
10997688
Filing Dt:
11/24/2004
Title:
CIRCUIT AND METHOD FOR SUPPLYING PROGRAMMING POTENTIAL AT VOLTAGES LARGER THAN BVDSS OF PROGRAMMING TRANSISTORS
5
Patent #:
Issue Dt:
07/03/2007
Application #:
11011752
Filing Dt:
12/14/2004
Publication #:
Pub Dt:
07/21/2005
Title:
METHOD AND APPARATUS TO DRIVE LED ARRAYS USING TIME SHARING TECHNIQUE
6
Patent #:
Issue Dt:
03/06/2007
Application #:
11011753
Filing Dt:
12/14/2004
Publication #:
Pub Dt:
07/21/2005
Title:
LAMP CURRENT CONTROL USING PROFILE SYNTHESIZER
7
Patent #:
Issue Dt:
02/27/2007
Application #:
11011754
Filing Dt:
12/14/2004
Publication #:
Pub Dt:
07/21/2005
Title:
INVERTER WITH TWO SWITCHING STAGES FOR DRIVING LAMP
8
Patent #:
Issue Dt:
09/04/2007
Application #:
11011760
Filing Dt:
12/14/2004
Publication #:
Pub Dt:
07/28/2005
Title:
CURRENT-MODE DIRECT-DRIVE INVERTER
9
Patent #:
Issue Dt:
11/21/2006
Application #:
11016699
Filing Dt:
12/17/2004
Title:
INTEGRATED MULTI-FUNCTION ANALOG CIRCUIT INCLUDING VOLTAGE, CURRENT, AND TEMPERATURE MONITOR AND GATE-DRIVER CIRCUIT BLOCKS
10
Patent #:
Issue Dt:
10/10/2006
Application #:
11021092
Filing Dt:
12/22/2004
Title:
POWER-UP AND POWER-DOWN CIRCUIT FOR SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT
11
Patent #:
Issue Dt:
09/26/2006
Application #:
11021472
Filing Dt:
12/23/2004
Publication #:
Pub Dt:
06/29/2006
Title:
NON-VOLATILE MEMORY CONFIGURATION SCHEME FOR VOLATILE-MEMORY-BASED PROGRAMMABLE CIRCUITS IN AN FPGA
12
Patent #:
Issue Dt:
10/03/2006
Application #:
11022331
Filing Dt:
12/21/2004
Publication #:
Pub Dt:
06/22/2006
Title:
VOLTAGE- AND TEMPERATURE-COMPENSATED RC OSCILLATOR CIRCUIT
13
Patent #:
Issue Dt:
12/23/2008
Application #:
11023295
Filing Dt:
12/27/2004
Publication #:
Pub Dt:
09/01/2005
Title:
METHOD AND APPARATUS TO CONTROL DISPLAY BRIGHTNESS WITH AMBIENT LIGHT CORRECTION
14
Patent #:
Issue Dt:
10/31/2006
Application #:
11026336
Filing Dt:
12/29/2004
Title:
NON-VOLATILE LOOK-UP TABLE FOR AN FPGA
15
Patent #:
Issue Dt:
11/04/2008
Application #:
11027788
Filing Dt:
12/29/2004
Publication #:
Pub Dt:
06/29/2006
Title:
ESD PROTECTION STRUCTURE FOR I/O PAD SUBJECT TO BOTH POSITIVE AND NEGATIVE VOLTAGES
16
Patent #:
Issue Dt:
09/11/2007
Application #:
11027789
Filing Dt:
12/29/2004
Title:
SYSTEM FOR SIGNAL ROUTING LINE AGGREGATION IN A FIELD-PROGRAMMABLE GATE ARRAY
17
Patent #:
Issue Dt:
05/01/2007
Application #:
11028471
Filing Dt:
12/31/2004
Title:
FIELD PROGRAMMABLE GATE ARRAY LONG LINE ROUTING NETWORK
18
Patent #:
Issue Dt:
04/12/2011
Application #:
11029297
Filing Dt:
01/04/2005
Publication #:
Pub Dt:
07/06/2006
Title:
ADAPTIVE EQUALIZATION WITH GROUP DELAY
19
Patent #:
Issue Dt:
03/21/2006
Application #:
11056957
Filing Dt:
02/11/2005
Title:
TILEABLE FIELD-PROGRAMMABLE GATE ARRAY ARCHITECTURE
20
Patent #:
Issue Dt:
12/27/2005
Application #:
11056983
Filing Dt:
02/11/2005
Title:
DEDICATED INPUT/OUTPUT FIRST IN/FIRST OUT MODULE FOR A FIELD PROGRAMMABLE GATE ARRAY
21
Patent #:
Issue Dt:
06/19/2007
Application #:
11056984
Filing Dt:
02/11/2005
Title:
BLOCK SYMMETRIZATION IN A FIELD PROGRAMMABLE GATE ARRAY
22
Patent #:
Issue Dt:
02/02/2010
Application #:
11060061
Filing Dt:
02/16/2005
Publication #:
Pub Dt:
03/02/2006
Title:
VARIABLE BANDWIDTH TRANSIMPEDANCE AMPLIFIER WITH ONE-WIRE INTERFACE
23
Patent #:
Issue Dt:
03/06/2007
Application #:
11071127
Filing Dt:
03/03/2005
Publication #:
Pub Dt:
09/01/2005
Title:
DEVICE FOR PROTECTING I/O LINES USING PIN OR NIP CONDUCTING LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSORS AND STEERING DIODES
24
Patent #:
Issue Dt:
08/01/2006
Application #:
11071128
Filing Dt:
03/03/2005
Publication #:
Pub Dt:
09/15/2005
Title:
UNI-DIRECTIONAL PIN OR NIP CONDUCTING LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSORS AND STEERING DIODES
25
Patent #:
Issue Dt:
01/16/2007
Application #:
11071513
Filing Dt:
03/03/2005
Publication #:
Pub Dt:
09/01/2005
Title:
BI-DIRECTIONAL PIN OR NIP LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSORS AND STEERING DIODES
26
Patent #:
Issue Dt:
10/24/2006
Application #:
11074922
Filing Dt:
03/07/2005
Publication #:
Pub Dt:
07/07/2005
Title:
MULTI-LEVEL ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY HAVING TRANSMITTERS AND RECEIVERS
27
Patent #:
Issue Dt:
06/24/2008
Application #:
11078952
Filing Dt:
03/10/2005
Title:
SWITCHING RATIO AND ON-STATE RESISTANCE OF AN ANTIFUSE PROGRAMMED BELOW 5 MA AND HAVING A TA OR TAN BARRIER METAL LAYER
28
Patent #:
Issue Dt:
09/18/2012
Application #:
11079323
Filing Dt:
03/14/2005
Publication #:
Pub Dt:
07/21/2005
Title:
METHOD OF FABRICATING A LIGHT-EMITTING DEVICE (LED) UTILIZING POWDER/PELLETIZED HOMOGENEOUSLY MIXED MOLDING COMPOUND
29
Patent #:
Issue Dt:
04/05/2011
Application #:
11084892
Filing Dt:
03/21/2005
Title:
AUTOMATIC GAIN CONTROL TECHNIQUE FOR CURRENT MONITORING IN CURRENT-MODE SWITCHING REGULATORS
30
Patent #:
Issue Dt:
04/15/2008
Application #:
11088621
Filing Dt:
03/23/2005
Publication #:
Pub Dt:
08/25/2005
Title:
BLOCK LEVEL ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY
31
Patent #:
Issue Dt:
09/26/2006
Application #:
11090246
Filing Dt:
03/25/2005
Publication #:
Pub Dt:
10/06/2005
Title:
FULL-BRIDGE AND HALF-BRIDGE COMPATIBLE DRIVER TIMING SCHEDULE FOR DIRECT DRIVE BACKLIGHT SYSTEM
32
Patent #:
Issue Dt:
06/13/2006
Application #:
11095294
Filing Dt:
03/31/2005
Title:
ZIGZAG TOPOLOGY FOR BALANCING CURRENT AMONG PARALLELED GAS DISCHARGE LAMPS
33
Patent #:
Issue Dt:
02/06/2007
Application #:
11095313
Filing Dt:
03/31/2005
Publication #:
Pub Dt:
10/05/2006
Title:
NESTED BALANCING TOPOLOGY FOR BALANCING CURRENT AMONG MULTIPLE LAMPS
34
Patent #:
Issue Dt:
01/25/2011
Application #:
11098960
Filing Dt:
04/05/2005
Publication #:
Pub Dt:
09/01/2005
Title:
NETWORK TIME TRANSFER
35
Patent #:
Issue Dt:
07/31/2007
Application #:
11099995
Filing Dt:
04/06/2005
Publication #:
Pub Dt:
10/13/2005
Title:
PRIMARY SIDE CURRENT BALANCING SCHEME FOR MULTIPLE CCF LAMP OPERATION
36
Patent #:
Issue Dt:
07/11/2006
Application #:
11120509
Filing Dt:
05/02/2005
Title:
REPEATABLE BLOCK PRODUCING A NON-UNIFORM ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY HAVING SEGMENTED TRACKS
37
Patent #:
Issue Dt:
10/24/2006
Application #:
11123733
Filing Dt:
05/05/2005
Publication #:
Pub Dt:
09/22/2005
Title:
METHOD AND APPARATUS OF MEMORY CLEARING WITH MONITORING RAM MEMORY CELLS IN A FIELD PROGRAMMABLE GATED ARRAY
38
Patent #:
Issue Dt:
10/10/2006
Application #:
11123734
Filing Dt:
05/05/2005
Publication #:
Pub Dt:
09/22/2005
Title:
FIELD-PROGRAMMABLE GATE ARRAY LOW VOLTAGE DIFFERENTIAL SIGNALING DRIVER UTILIZING TWO COMPLIMENTARY OUTPUT BUFFERS
39
Patent #:
Issue Dt:
07/17/2007
Application #:
11128682
Filing Dt:
05/13/2005
Title:
CHIP CARRIER SUBSTRATE WITH A LAND GRID ARRAY AND EXTERNAL BOND TERMINALS
40
Patent #:
Issue Dt:
12/12/2006
Application #:
11128743
Filing Dt:
05/13/2005
Title:
METHOD FOR USING A CHIP CARRIER SUBSTRATE WITH A LAND GRID ARRAY AND EXTERNAL BOND TERMINALS
41
Patent #:
Issue Dt:
03/11/2008
Application #:
11145042
Filing Dt:
06/03/2005
Publication #:
Pub Dt:
10/06/2005
Title:
SPLIT-GATE POWER MODULE FOR SUPPRESSING OSCILLATION THEREIN
42
Patent #:
Issue Dt:
07/13/2010
Application #:
11145877
Filing Dt:
06/06/2005
Publication #:
Pub Dt:
01/12/2006
Title:
DUAL-SLOPE BRIGHTNESS CONTROL FOR TRANSFLECTIVE DISPLAYS
43
Patent #:
Issue Dt:
05/06/2008
Application #:
11152018
Filing Dt:
06/13/2005
Title:
NON-VOLATILE PROGRAMMABLE MEMORY CELL AND ARRAY FOR PROGRAMMABLE LOGIC ARRAY
44
Patent #:
Issue Dt:
08/03/2010
Application #:
11152019
Filing Dt:
06/13/2005
Title:
ISOLATED-NITRIDE-REGION NON-VOLATILE MEMORY CELL AND FABRICATION METHOD
45
Patent #:
Issue Dt:
04/01/2008
Application #:
11154134
Filing Dt:
06/15/2005
Publication #:
Pub Dt:
12/29/2005
Title:
ADHESION AND/OR ENCAPSULATION OF SILICON CARBIDE-BASED SEMICONDUCTOR DEVICES ON CERAMIC SUBSTRATES
46
Patent #:
Issue Dt:
09/16/2008
Application #:
11154488
Filing Dt:
06/16/2005
Publication #:
Pub Dt:
12/21/2006
Title:
SLOPE COMPENSATION CIRCUIT
47
Patent #:
Issue Dt:
10/23/2007
Application #:
11155005
Filing Dt:
06/15/2005
Publication #:
Pub Dt:
12/21/2006
Title:
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
48
Patent #:
Issue Dt:
06/05/2007
Application #:
11161946
Filing Dt:
08/23/2005
Title:
TWO CHANNEL DIGITAL PHASE DETECTOR
49
Patent #:
Issue Dt:
04/15/2008
Application #:
11171488
Filing Dt:
06/29/2005
Title:
ARCHITECTURE FOR FACE-TO-FACE BONDING BETWEEN SUBSTRATE AND MULTIPLE DAUGHTER CHIPS
50
Patent #:
Issue Dt:
01/09/2007
Application #:
11171489
Filing Dt:
06/29/2005
Title:
METHOD FOR ERASING PROGRAMMABLE INTERCONNECT CELLS FOR FIELD PROGRAMMABLE GATE ARRAYS USING REVERSE BIAS VOLTAGE
51
Patent #:
Issue Dt:
05/29/2007
Application #:
11171510
Filing Dt:
06/29/2005
Title:
INTEGRATED CIRCUIT WAFER WITH INTER-DIE METAL INTERCONNECT LINES TRAVERSING SCRIBE-LINE BOUNDARIES
52
Patent #:
Issue Dt:
02/06/2007
Application #:
11181503
Filing Dt:
07/14/2005
Publication #:
Pub Dt:
01/26/2006
Title:
PUSH-PULL DRIVER WITH NULL-SHORT FEATURE
53
Patent #:
Issue Dt:
02/06/2007
Application #:
11181505
Filing Dt:
07/14/2005
Publication #:
Pub Dt:
02/02/2006
Title:
INCREMENTAL DISTRIBUTED DRIVER
54
Patent #:
Issue Dt:
06/17/2008
Application #:
11181649
Filing Dt:
07/14/2005
Title:
RAMP GENERATOR WITH FAST RESET
55
Patent #:
Issue Dt:
12/25/2007
Application #:
11183554
Filing Dt:
07/18/2005
Publication #:
Pub Dt:
11/16/2006
Title:
SHOOT-THROUGH PREVENTION CIRCUIT FOR PASSIVE LEVEL-SHIFTER
56
Patent #:
Issue Dt:
12/09/2008
Application #:
11185426
Filing Dt:
07/19/2005
Title:
APPARATUS AND METHOD FOR REDUCING LEAKAGE OF UNUSED BUFFERS IN AN INTEGRATED CIRCUIT
57
Patent #:
Issue Dt:
08/25/2009
Application #:
11185427
Filing Dt:
07/19/2005
Title:
METHOD FOR SECURE DELIVERY OF CONFIGURATION DATA FOR A PROGRAMMABLE LOGIC DEVICE
58
Patent #:
Issue Dt:
04/07/2009
Application #:
11187068
Filing Dt:
07/22/2005
Publication #:
Pub Dt:
11/17/2005
Title:
FIELD PROGRAMMABLE GATE ARRAY AND MICROCONTROLLER SYSTEM-ON-A-CHIP
59
Patent #:
Issue Dt:
01/30/2007
Application #:
11189199
Filing Dt:
07/25/2005
Title:
DELAY LOCKED LOOP FOR AND FPGA ARCHITECTURE
60
Patent #:
Issue Dt:
07/01/2008
Application #:
11195002
Filing Dt:
08/01/2005
Title:
REPROGRAMMABLE METAL-TO-METAL ANTIFUSE EMPLOYING CARBON-CONTAINING ANTIFUSE MATERIAL
61
Patent #:
Issue Dt:
10/09/2007
Application #:
11202686
Filing Dt:
08/12/2005
Publication #:
Pub Dt:
12/08/2005
Title:
ARCHITECTURE FOR ROUTING RESOURCES IN A FIELD PROGRAMMABLE GATE ARRAY
62
Patent #:
Issue Dt:
04/15/2008
Application #:
11210492
Filing Dt:
08/23/2005
Title:
AMORPHOUS CARBON METAL-TO-METAL ANTIFUSE WITH ADHESION PROMOTING LAYERS
63
Patent #:
Issue Dt:
07/29/2008
Application #:
11218331
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
06/15/2006
Title:
DATA DE-SKEW METHOD AND SYSTEM
64
Patent #:
Issue Dt:
06/03/2008
Application #:
11219597
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
09/14/2006
Title:
METHOD AND APPARATUS FOR UNIVERSAL PROGRAM CONTROLLED BUS ARCHITECTURE
65
Patent #:
Issue Dt:
04/14/2009
Application #:
11221609
Filing Dt:
09/07/2005
Title:
DIGITAL AUTOMATIC POWER CONTROL LOOP FOR CONTINUOUS AND BURST MODE APPLICATIONS
66
Patent #:
Issue Dt:
06/26/2007
Application #:
11231320
Filing Dt:
09/20/2005
Publication #:
Pub Dt:
05/11/2006
Title:
CROSSPOINT SWITCH WITH SWITCH MATRIX MODULE
67
Patent #:
Issue Dt:
08/04/2009
Application #:
11233180
Filing Dt:
09/21/2005
Publication #:
Pub Dt:
05/03/2007
Title:
RF POWER TRANSISTOR PACKAGE
68
Patent #:
Issue Dt:
07/18/2006
Application #:
11233290
Filing Dt:
09/21/2005
Publication #:
Pub Dt:
04/13/2006
Title:
ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS
69
Patent #:
Issue Dt:
07/17/2007
Application #:
11233396
Filing Dt:
09/21/2005
Publication #:
Pub Dt:
03/22/2007
Title:
NON-VOLATILE PROGRAMMABLE MEMORY CELL FOR PROGRAMMABLE LOGIC ARRAY
70
Patent #:
Issue Dt:
09/19/2006
Application #:
11238311
Filing Dt:
09/29/2005
Publication #:
Pub Dt:
02/09/2006
Title:
SYSTEMS FOR AUTO-INTERLEAVING SYNCHRONIZATION IN A MULTIPHASE SWITCHING POWER CONVERTER
71
Patent #:
Issue Dt:
01/22/2008
Application #:
11240115
Filing Dt:
09/30/2005
Publication #:
Pub Dt:
02/02/2006
Title:
SQUARE WAVE DRIVE SYSTEM
72
Patent #:
Issue Dt:
11/27/2007
Application #:
11251074
Filing Dt:
10/13/2005
Title:
VOLATILE DATA STORAGE IN A NON-VOLATILE MEMORY CELL ARRAY
73
Patent #:
Issue Dt:
10/09/2007
Application #:
11255563
Filing Dt:
10/21/2005
Publication #:
Pub Dt:
02/23/2006
Title:
APPARATUS AND METHOD FOR STRIKING A FLUORESCENT LAMP
74
Patent #:
Issue Dt:
04/22/2008
Application #:
11279046
Filing Dt:
04/07/2006
Publication #:
Pub Dt:
08/17/2006
Title:
INTEGRATED CIRCUIT INCLUDING PROGRAMMABLE LOGIC AND EXTERNAL-DEVICE CHIP-ENABLE OVERRIDE CONTROL
75
Patent #:
Issue Dt:
03/11/2008
Application #:
11281253
Filing Dt:
11/16/2005
Publication #:
Pub Dt:
05/17/2007
Title:
BIT LINE PRE-SETTLEMENT CIRCUIT AND METHOD FOR FLASH MEMORY SENSING SCHEME
76
Patent #:
Issue Dt:
03/03/2009
Application #:
11286144
Filing Dt:
11/23/2005
Publication #:
Pub Dt:
06/08/2006
Title:
JUNCTION TERMINATION STRUCTURES FOR WIDE-BANDGAP POWER DEVICES
77
Patent #:
Issue Dt:
09/05/2006
Application #:
11295889
Filing Dt:
12/06/2005
Publication #:
Pub Dt:
04/27/2006
Title:
DEDICATED INPUT/OUTPUT FIRST IN/FIRST OUT MODULE FOR A FIELD PROGRAMMABLE GATE ARRAY
78
Patent #:
Issue Dt:
06/05/2007
Application #:
11297088
Filing Dt:
12/07/2005
Publication #:
Pub Dt:
04/20/2006
Title:
SYNCHRONOUS FIRST-IN/FIRST-OUT BLOCK MEMORY FOR A FIELD PROGRAMMABLE GATE ARRAY
79
Patent #:
Issue Dt:
08/05/2008
Application #:
11299248
Filing Dt:
12/09/2005
Publication #:
Pub Dt:
05/04/2006
Title:
ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS
80
Patent #:
Issue Dt:
09/11/2007
Application #:
11303863
Filing Dt:
12/16/2005
Publication #:
Pub Dt:
06/21/2007
Title:
ADDRESS TRANSITION DETECTOR FOR FAST FLASH MEMORY DEVICE
81
Patent #:
Issue Dt:
05/26/2009
Application #:
11303865
Filing Dt:
12/16/2005
Title:
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
82
Patent #:
Issue Dt:
04/22/2008
Application #:
11319751
Filing Dt:
12/27/2005
Title:
PROGRAMMING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY-BASED PROGRAMMABLE LOGIC DEVICE
83
Patent #:
Issue Dt:
10/24/2006
Application #:
11323417
Filing Dt:
12/30/2005
Publication #:
Pub Dt:
06/15/2006
Title:
DEGLITCHING CIRCUITS FOR A RADIATION-HARDENED STATIC RANDOM ACCESS MEMORY BASED PROGRAMMABLE ARCHITECTURE
84
Patent #:
Issue Dt:
10/24/2006
Application #:
11326543
Filing Dt:
01/04/2006
Publication #:
Pub Dt:
06/01/2006
Title:
FLOOR PLAN FOR SCALABLE MULTIPLE LEVEL TAB ORIENTED INTERCONNECT ARCHITECTURE
85
Patent #:
Issue Dt:
06/05/2007
Application #:
11330497
Filing Dt:
01/11/2006
Title:
DIFFERENTIAL OPTO-ELECTRONICS TRANSMITTER
86
Patent #:
Issue Dt:
01/02/2007
Application #:
11335396
Filing Dt:
01/18/2006
Publication #:
Pub Dt:
06/01/2006
Title:
TILEABLE FIELD-PROGRAMMABLE GATE ARRAY ARCHITECTURE
87
Patent #:
Issue Dt:
04/05/2011
Application #:
11336396
Filing Dt:
01/20/2006
Title:
FIELD PROGRAMMABLE GATE ARRAY INCLUDING A NON-VOLATILE USER MEMORY AND METHOD FOR PROGRAMMING
88
Patent #:
Issue Dt:
04/29/2008
Application #:
11345549
Filing Dt:
01/31/2006
Publication #:
Pub Dt:
06/08/2006
Title:
PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL
89
Patent #:
Issue Dt:
02/06/2007
Application #:
11367081
Filing Dt:
03/02/2006
Publication #:
Pub Dt:
07/06/2006
Title:
APPARATUS AND METHOD OF ERROR DETECTION AND CORRECTION IN A RADIATION-HARDENED STATIC RANDOM ACCESS MEMORY FIELD-PROGRAMMABLE GATE ARRAY
90
Patent #:
Issue Dt:
05/20/2008
Application #:
11387636
Filing Dt:
03/22/2006
Title:
CLOCK TREE NETWORK IN A FIELD PROGRAMMABLE GATE ARRAY
91
Patent #:
Issue Dt:
09/17/2013
Application #:
11388515
Filing Dt:
03/24/2006
Publication #:
Pub Dt:
10/12/2006
Title:
IMPLANTABLE RF TELEMETRY DEVICES WITH POWER SAVING MODE
92
Patent #:
Issue Dt:
11/07/2006
Application #:
11410413
Filing Dt:
04/24/2006
Publication #:
Pub Dt:
08/24/2006
Title:
INTER-TILE BUFFER SYSTEM FOR A FIELD PROGRAMMABLE GATE ARRAY
93
Patent #:
Issue Dt:
05/01/2007
Application #:
11410415
Filing Dt:
04/24/2006
Publication #:
Pub Dt:
08/31/2006
Title:
SRAM BUS ARCHITECTURE AND INTERCONNECT TO AN FPGA
94
Patent #:
Issue Dt:
01/20/2009
Application #:
11414128
Filing Dt:
04/28/2006
Publication #:
Pub Dt:
05/10/2007
Title:
FRONT SIDE ILLUMINATED PHOTODIODE WITH BACKSIDE BUMP
95
Patent #:
Issue Dt:
04/29/2008
Application #:
11426158
Filing Dt:
06/23/2006
Publication #:
Pub Dt:
11/02/2006
Title:
THREE INPUT FIELD PROGRAMMABLE GATE ARRAY LOGIC CIRCUIT CONFIGURABLE AS A THREE INPUT LOOK UP TABLE, A D-LATCH OR A D FLIP-FLOP
96
Patent #:
Issue Dt:
06/10/2008
Application #:
11426541
Filing Dt:
06/26/2006
Title:
REPEATABLE BLOCK PRODUCING A NON-UNIFORM ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY HAVING SEGMENTED TRACKS
97
Patent #:
Issue Dt:
05/29/2007
Application #:
11427456
Filing Dt:
06/29/2006
Title:
SRAM CELL CONTROLLED BY FLASH MEMORY CELL
98
Patent #:
Issue Dt:
11/20/2007
Application #:
11427717
Filing Dt:
06/29/2006
Title:
CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
99
Patent #:
Issue Dt:
04/03/2007
Application #:
11428944
Filing Dt:
07/06/2006
Title:
DEDICATED INPUT/OUTPUT FIRST IN/FIRST OUT MODULE FOR A FIELD PROGRAMMABLE GATE ARRAY
100
Patent #:
Issue Dt:
11/28/2006
Application #:
11432425
Filing Dt:
05/10/2006
Publication #:
Pub Dt:
09/14/2006
Title:
ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS
Assignor
1
Exec Dt:
01/15/2016
Assignees
1
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
2
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
3
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
4
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
5
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
6
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
7
ONE ENTERPRISE
ALISO VIEJO, CALIFORNIA 92656
Correspondence name and address
ELAINE CARRERA, LEGAL ASSISTANT
80 PINE STREET
C/O CAHILL GORDON & REINDEL LLP
NEW YORK, NY 10005

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